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| preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice preliminary specification - 1 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 h ardware m onitor w ith i ntegrated f an c ontrol ASC7621 p roduct s pecification product description the ASC7621 has a two wire digital interface compatible with smbus 2.0. using a 10-bit ? - adc, the ASC7621 measures the temper ature of two remote diode connected transistors as well as its own die. support for platform environmental control interface (peci) is included. using temperature information from these four zones, an automatic fan speed control algorithm is employed to minimize acoustic impact while achieving recommended cpu temperature under vary ing operational loads. to set fan speed, the ASC7621 has three independent pulse width modulation (pwm) outputs that are controlled by one, or a combination of three, temperature zones. both high- and low-frequency pwm ranges are supported. the ASC7621 also includes a digital filter that can be invoked to smooth temperature readings for better control of fan speed and minimum acoustic impact. the ASC7621 has tachometer inputs to measure fan speed on up to four fans. limit and status registers for all measured values are included to alert the system host that any measurements are outside of programmed limit s via status registers. system voltages of vccp, 2.5v, 3.3v, 5.0v, and 12v motherboard power are monitored efficiently with internal scaling resistors. features ? supports peci interface and monitors internal and remote thermal diodes ? 2-wire, smbus 2.0 compliant, serial interface ? 10-bit ? -adc ? monitors vccp, 2.5v, 3.3v, 5.0v, and 12v motherboard/processor supplies ? programmable autonomous fan control based on temperature readings ? noise filtering of tem perature reading for fan speed control ? 0.25 c digital temperature sensor resolution ? 3 pwm fan speed control outputs for 2-, 3- or 4- wire fans and up to 4 fan tachometer inputs ? enhanced measured temperature to temperature zone assignment. ? provides high and low pwm frequency ranges ? 3 gpio pins for custom use ? 24-lead qsop package measurement system temperature: ? 0.25c resolution, 2c accuracy on remote diode ? 0.25c resolution, 3c accuracy on local sensor ? temperature measurement range on remote sensor ?55c to +125c using 2?s complement coding. voltage: ? 10-bit resolution, 2% (tue) fan tachometer: ? 16-bit count of 90khz clock periods limit alarms for all measured values applications ? desktop computers ? motherboards and graphics cards ? microprocessor based equipment (e.g. base- stations, routers, atms, point of sales) connection diagram ordering information part number package temperature range and operating voltage marking how supplied ASC7621qs24 24-lead qsop 0c to +120c, 3.3v ASC7621 ayww 2500 units tape & reel ayww ? assembly site, year, workweek 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 smbdat smbclk gnd 3.3v gpio2 gpio1 peci vtt tach3 pwm2 tach1 tach2 pwm1/ xtestout vccp 2.5v 12v 5v gpio3 remote 1+ remote 1- remote 2+ remote 2- tach4/ addressselect pwm3/ add ress enable ASC7621
preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 2 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 block diagram figure 1 block diagram pwm3/ addressenable gpio register gpio1 gpio2 gpio3 fan speed counter tach1 tach2 tach3 tach4/ address select internal temp sensor 3.3v 5v 12v 2.5v vccp remote 1+ remote 1- remote 2- remote 2+ stepping and device id registers address pointer registers 10-bit ? -adc bandgap reference serial bus interface voltage fan speed temperature, and limit value registers smbdat smbclk limit comparators status registers configuration registers spike smoothing fan tmin/trange/ hyst registers fan characteristics fan speed config registers fan pwm control & pwm value registers pwm1 pwm2 input attenuators, external diode signal conditioning, and analog multiplexer peci interface peci vtt preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 3 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 pin descriptions symbol pin type name and function/connection smbdat 1 digital i/o (open-drain) system management bus data. open-drain output. 5v tolerant, smbus 2.0 compliant. smbus smbclk 2 digital input system management bus clock. tied to open-drain output. 5v tolerant, smbus 2.0 compliant. peci 7 digital i/o platform environmental control interface (peci). peci 1.0 compliant, cpu digital thermometer input peci vtt 8 analog input peci reference voltage. 3.3v 4 power +3.3v pin. can be powered by +3.3v standby power if monitoring in low power states is required. this pin should be bypassed with a 0.1 f capacitor in parallel with 100pf. a bulk capacitance of approximately 10 f needs to be in near vicinity of the ASC7621. power gnd 3 ground ground for all analog and digital circuitry. 5v 20 analog input analog input for +5v monitoring. 12v 21 analog input analog input for +12v monitoring. 2.5v 22 analog input analog input for +2.5v monitoring.. voltage inputs vccp 23 analog input analog input for vccp (processor voltage) monitoring. remote 1+ 18 remote thermal diode positive input positive input (current source) from the first remote thermal diode serves as the positive input into the a/d. connected to thermda pin of pentium processor. remote 1- 17 remote thermal diode negative input negative input (current sink) from the first remote thermal diode serves as the negative input into the a/d. connected to thermdc pin of pentium processor. remote 2+ 16 remote thermal diode positive output positive input (current source) from the second remote thermal diode serves as the pos itive input into the a/d. connected to the base of a diode connected mmbt3904 npn transistor. remote remote 2- 15 remote thermal diode negative input negative input (current sink) from the second remote thermal diode serves as the neg ative input into the a/d. connected to the emitter of a diode connected mmbt3904 npn transistor. tach1 11 digital input input for monitoring tachometer output of fan 1. tach2 12 digital input input for monitoring tac hometer output of fan 2. tach3 9 digital input input for monitoring tachomet er output of fan 3. during power-up, if held low through a 10k resistor, smbus address may be selected based on the state of tach4 pin. fan tachometer inputs tach4/addressselect 14 digital input input for monitoring tachometer output of fan 4. if in address select mode, determines the smbus address of ASC7621. pwm1/xtestout 24 digital open- drain output fan speed control 1. when in xor tree test mode, functions as xor tree output. pwm2 10 digital open- drain output fan speed control 2. fan control pwm3/address enable 13 digital open- drain output fan speed control 3. pull to ground at power on to enable address select mode (address select pin controls smbus address of the device). preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 4 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 symbol pin type name and function/connection gpio1 6 digital i/o alert out / zone # th erm out. default is gpio input gpio2 5 digital i/o alert out / zone # th erm out. default is gpio input gpio gpio3 19 digital i/o alert out / zone # th erm out. default is gpio input absolute maximum ratings 1 parameter rating supply voltage, v dd 3.6v voltage on any digital input or output pin other than pwm outputs -0.3v to v dd +0.3v voltage on pwm outputs -0.3v to 5.5v voltage on 12v analog input -0.5v to 16v voltage on 5v analog input -0.5v to 6.5v voltage on remote 1 +, remote 2 + -0.5v to (v dd + 0.50v) voltage on other analog inputs -0.5v to 6.0v current on remote 1 -, remote 2 - 1ma input current on any pin 2 5ma package input current 2 20ma package dissipation at t a = 25 c see (note 3) storage temperature -65 c to +150 c human body model 4000 v machine model 250 v esd 4 charged device model 2000v notes: 1. absolute maximum ratings are limits beyond which operation may cause permanent damage to the device. these are stress ratings only; functional operation at or above these limits is not implied. 2. when the input voltage (v in ) at any pin exceeds the power supplies (v in < gnd or v in > v dd ), the current at that pin should be limited to 5ma. the 20ma maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5ma to four. parasitic components and/or esd protection circuitry are present on the ASC7621 pins. care should be taken not to forward bias the parasitic diode present on pins d+ and d-. doing so by more than 50mv may corrupt temperature measurements. operating ratings 1 parameter rating ASC7621 operating temperature range, ambient temperature, t min to t max 0 c t a +120 c remote diode temperature range -55 c t d +125 c supply voltage (3.3v nominal) +3.0v to +3.6v v in voltage range +12v v in -0.05v to 16v +5v v in -0.05v to 6.5v +3.3v v in 3.0v to 4.4v vccp and all other inputs -0.05v to v dd + 0.05v typical supply current 1.8ma 3. thermal resistance junction-to-ambient when attached to a double-sided printed circuit board with 1oz. foil is 115 c/w 4. human body model: 100pf capacitor discharged through a 1.5k ? resistor into each pin. machine model: 200pf capacitor discharged directly into each pin. charged-device model is per jesd22- c101c. preliminary specification ? s ubject to change without notice preliminary specific ation ? subject to change without notice - 5 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 dc electrical characteristics 5 the following specifications apply for v dd = 3.0v to 3.6v, and all analog input source impedance r s = 50 ? unless otherwise specified in conditions. boldface limits apply for t a = t j over t min to t max ; all other limits t a = t j = 25 c. t a is the ambient temperat ure of the ASC7621; t j is the junction temperature of ASC7621; t d is the remote thermal diode junction temperature. specificati ons subject to change without notice parameter conditions min typ max units power supply characteristics converting, interface and fans inactive, peak current 1.8 3.5 ma(max) supply current converting, interface and fans inactive, average current 0.5 ma power-on reset threshold voltage 1.6 2.8 v temperature to digital converter characteristics resolution 0.25 10 c bits 0c t a +100c, 0c t d +100c, 3v v dd 3.6v 2 c remote sensor accuracy 6 0c t a +120c, -55c t d +125c, 3v v dd 3.6v 3 c temperature accuracy using internal diode 7 0c t a +120c, 3v v dd 3.6v 1 3 c high level 96 a(max) external diode current source i ds low level 6 a external diode current ratio 16 analog to digital converter characteristics total unadjusted error 8 tue 2 %(max) differential non-linearity dnl 1 lsb power supply sensitivity 1 %/v total monitoring cycle time 9 all voltage and temperature readings 200 250 ms (max) input resistance, all analog inputs 140 210 400 k ? digital output: pwm1, pwm2, pwm3, xtestout logic low sink current i ol v ol = 0.4v 8 ma (min) logic low level v ol i out = +8ma 0.4 v (max) smbus open-drain output: smbdat logic low output voltage v ol i out = +4ma 0.4 v (max) high level output current i oh v out = v+ 0.1 10 a(max) smbus inputs: smbclk, smbdat logic input high voltage v ih 2.1 v (min) logic input low voltage v il 0.8 v (max) logic input hysteresis voltage v hyst 300 mv digital inputs: all logic input high voltage v ih 2.1 v (min) preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 6 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 parameter conditions min typ max units logic input low voltage v il 0.8 v (max) logic input threshold voltage v th 1.5 v logic high input current i ih v in = v+ 0.005 10 a(max) logic low input current i il v in = gnd -0.005 -10 a(max) digital input capacitance c in 20 pf ac electrical characteristics the following specifications apply for v dd = 3.0v to 3.6v unless otherwise specified in conditions. boldface limits apply for t a = t j over t min to t max ; all other limits t a = t j = 25 c. parameter conditions min typ max units tachometer fan full-scale count 65535 (max) fan counter clock frequency 90 khz fan count conversion time 0.3 1.0 sec(max) fan pwm output low-frequency range 10 94 hz hz frequency range high-frequency range 23 30 khz khz duty-cycle range 0 to 100 %(max) duty-cycle resolution (8-bits) 0.3906 %/count spin-up time interval range 0 4000 ms ms logic electrical characteristics (t a = 25 c, v dd = 3.3v unless otherwise noted) parameter symbol conditions min typ max units input voltage logic high v ih 3v v dd 3.6v 2.1 v input voltage logic low v il 3v v dd 3.6v 0.8 v input leakage current i in v in = 0v or 5.5v, 0c t a +125c 1.0 a smbus output sink current i ol t a = 25 c, v ol = 0.6v 6 ma smbus logic input current i ih, i il -1 +1 a output leakage current i oh v oh = v dd = 5.5v 0.1 1 a output transition time t f c l = 400pf, i ol = -3ma 250 ns input capacitance c in all digital inputs 5 pf preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 7 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 serial port timing (t a = 25 c, v dd = 3.3v unless otherwise noted, guarant eed by design, not production tested) parameter symbol min typ max units scl operating frequency f scl 400 khz scl clock transition time t t:lh , t t:hl 300 ns scl clock low period t low 1.3 s scl clock high period t high 0.6 50 s bus free time between a stop and a new start condition t buf 1.3 s data in set-up to scl high t su:dat 100 ns data out stable after scl low t hd:dat 300 ns scl low set-up to sda low (repeated start condition) t su:sta 600 ns scl high hold after sda low (start condition) t hd:sta 600 ns sda high after scl high (stop condition) t su:sto 600 ns time in which ASC7621 must be operational after a power-on reset t por 500 ms smbus time-out before device communication interface reset 10 t timeout 25 35 ms notes (cont?d): 5. these specifications are guaranteed only for the test conditions listed. 6. the accuracy of the ASC7621 is guaranteed when using the ther mal diode of intel pentium 4, 65nm processors or any thermal diode with a non-ideality of 1.009 and series resistance of 4.52 ? . when using a 2n3904 type transistor or an cpu with a different non-ideality the error band will be typically shi fted depending on transistor diode or cpu characteristics. see applications section for details. 7. accuracy (expressed in c) = difference between the ASC7621 reported output temperature and the temperature being measured. local temperature accuracy does not include the effect s of self-heating. the rise in temperature due to self-heatin g is the product of the internal power dissipation of the ASC7621 and the thermal resistance. see (note 3) for the thermal resistance to be used in the self-heating calculation. 8. tue, total unadjusted error, includes adc gain, offset, li nearity and reference errors. tue is defined as the ?actual v in ? to achieve a given code transit ion minus the ?theoretical v in ? for the same code. therefore, a positive error indicates that the input voltage is greater than the theoretical input voltage for a giv en code. if the theoretical input voltage was applied to an asc 7621 that has positive error, the ASC7621?s reading would be less than the theoretical. 9. this specification is prov ided only to indicate how often temperature and voltage data is updated. the ASC7621 can be read at any time without regard to conversion stat e (and will yield last conversion result). 10. holding the smbclk line low for a time interval greater than t timeout will reset the ASC7621?s smbus state machine, therefore setting the smbdat pin to a high impedance state. t hd:sta t su:sto t su:dat scl sd a t buf t su:sta t hd:dat scl sda data out 10 10 90 t t:lh t t:hl t low t high 90 preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 8 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 control communication smbus the ASC7621 is compatible with devices that are compliant to the smbus 2.0 specifications. more information on this bus can be found at http://www.smbus.org/ . compatibility of smbus2.0 to other buses is discussed in the smbus 2.0 specification. general operation writing to and reading from the ASC7621 registers is accomplished via the smbus-compatible two-wire serial interface. smbus protocol r equires that one device on the bus initiate and control all re ad and write operations. this device is called the ?master? device. the master device also generates the scl signal that is the clock signal for all other devices on the bus. all other devices on the bus are called ?slave? devices. the ASC7621 is a slave device. both the master and slave devices can send and receive data on the bus. during smbus operations, one data bit is transmitted per clock cycle. all smbus operations follow a repeating nine clock-cycle pattern that consists of eight bits (one byte) of transmitted data followed by an acknowledge (ack) or not acknowledge (nack) from the receiving device. note that there are no unused clock cycles during any operation? therefore there must be no br eaks in the stream of data and acks / nacks during data transfers. for most operations, smbus protocol requires the sda line to remain stable (unmoving) whenever scl is high ? i.e. any transitions on the sda line can only occur when scl is low. the exceptions to this rule are when the master device issues a start or stop conditi on. note that the slave device cannot issue a start or stop condition. smbus definitions the following are definitions for some general smbus terms: start condition: this condition occurs when the sda line transitions from high to low while scl is high. the master device uses this condition to i ndicate that a data transfer is about to begin. stop condition: this condition occurs when the sda line transitions from low to high wh ile scl is high. the master device uses this condition to signal the end of a data transfer. acknowledge and not acknowledge: when data are transferred to the slave device it sends an ?acknowledge? (ack) after receiving each byte. the receiving device sends an ack by pulling sda low for one clock. following the last byte, a master device sends a "not acknowledge" (nack) followed by a stop condition. a nack is indicated by forcing sda high during the clock after the last byte. slave address ASC7621 is designed to be used primarily in desktop systems that require only one monitoring device. if only one ASC7621 is used on the motherboard, the designer should be sure that the addressenable /pwm3 pin is high during the first smbus communication addressing the ASC7621. addressenable /pwm3 is an open drain i/o pin that at power-on defaults to the input state of addressenable . a maximum of 10k pull-up resistance on addressenable /pwm3 is required to assure that the smbus address of the device will be locked at 010 1110b, which is the default address of the ASC7621. during the first smbus communication tach4 and pwm3 can be used to change the smbus address of the ASC7621 to 0101101b or 0101100b. ASC7621 address selection procedure: a 10k ? pull-down resistor to ground on the addressenable /pwm3 pin is required. upon power up, the ASC7621 will be placed into addressenable mode and assign itself on smbus address according to the stat e of the address select input. the ASC7621 will latch the address during the first valid smbus transaction in which the first five bits of the targeted address matc h those of the ASC7621 address, 0 1011b. this feature eliminates the possibility of a glitch on the smbus interfering with address selection. when the addressenable /pwm3 pin is not used to change the smbus address of the ASC7621, it will remain in a high state until the first communication with the ASC7621. after the first smbus transaction is completed pwm3 and tach4 will return to normal operation. smbus address address enable address select board imple- mentation binary hex 0 0 both pins pulled to ground through a 10 k ? resistor 010 1100 2ch 0 1 address select pulled to 3.3v and addressenable pulled to gnd through a 10 k ? resistor 010 1101 2dh 1 x addressenable pulled to 3.3v through a 10 k ? resistor 010 1110 2eh preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 9 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 in this way, up to three ASC7621 devices can exist on a smbus at any time. multiple ASC7621 devices can be used to monitor additional processors in the temperature zones. when using the non-default addresses, additional circuitry will be required if tach4 and pwm3 require to function correctly. such circuitry could consist of gpio pins from a micro-controller. during the first communication the micro-controller would drive the addressenable and address select pins to the proper state for the required address. after the first smbus communication the micro-controller would drive its pins into tri-state allowing tach4 and pwm3 to operate correctly. writing to and reading from the ASC7621 all read and write operations must begin with a start condition generated by the mast er device. after the start condition, the master devic e must immediately send a slave address (7-bits) followed by a r/ w bit. if the slave address matches the address of the ASC7621, it sends an ack by pulling the sda line low for one clock. read or write operations may contain one- or two-bytes. see figures 2 through 6 for timing diagrams for all ASC7621 operations. setting the register address pointer for all operations, the address pointer stored in the address pointer register must be pointing to the register address that is going to be written to or read from. this register?s content is automatically set to the value of the first byte following the r/ w bit being set to 0. after the ASC7621 sends an ack in response to receiving the address and r/ w bit, the master device must transmit an appropriate 8-bit address pointer value as explained in the registers section of this data sheet. the ASC7621 will send an ack after receiving the new pointer data. the register address pointer set operation is illustrated in figure 2. if the address pointer is not a valid address the ASC7621 will internally terminate the operation. also recall that the address register reta ins the current address pointer value between operations. ther efore, once a register is being pointed to, subsequent read operations do not require another address pointer set cycle. writing to registers all writes must start with a pointer set as described previously, even if the pointer is already pointing to the desired register. the sequence is described in figure 2. immediately following the pointer set, the master must begin transmitting the data to be written. after transmitting each byte of data, the master must release the sda line for one clock to allow the ASC7621 to acknowledge receiving the byte. the write operation should be terminated by a stop condition from the master. reading from registers to read from a register other than the one currently being pointed to by the address pointer register, a pointer set sequence to the desired register must be done as described previously. immediately following the pointer set, the master must perform a repeat start condition that indicates to the ASC7621 that a read is about to occur. it is important to note that if the repeat start condition does not occur, the ASC7621 will assume that a write is taking place, and the selected register will be overwritten by the upcoming data on the data bus. the read sequence is described in figure 4. after the start condition, the master must again send the device address and read/write bit. this time the r/ w bit must be set to 1 to indicate a read. the rest of the read cycle is the same as described in the previous paragraph for reading from a preset pointer location. if the pointer is already pointing to the desired register, the master can read from that register by setting the r/ w bit (following the slave address) to a 1. after sending an ack, the ASC7621 will begin transmitting data during the following clock cycle. after receiving the 8 data bits, the master device should respond with a nack followed by a stop condition. if the master is reset while the ASC7621 is in the process of being read, the master should perform an smbus reset. this is done by holding the clock low for more than 35ms, allowing all smbus devices to be reset. this follows the smbus 2.0 specific ation of 25-35ms. when the ASC7621 detects an smbus reset, it will prepare to accept a new start sequence and resume communication from a known state. preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 10 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 note: the following figures assume that device address 2ch has been chosen by the user via address selection. a7 a6 a5 a4 a3 a2 a1 a0 start smbus device address byte (2ch) register address byte a a ack from ASC7621 ack from ASC7621 scl sda 0 1 9 1 9 a7 a6 a5 a4 a3 a2 a1 a0 start smbus device address byte (2ch) register address byte r/w a a ack from ASC7621 ack from ASC7621 scl 1 9 1 9 stop by master 1 9 d7 d6 d5 d4 d3 d2 d1 d0 register data byte a ack from ASC7621 stop by master r/w sda d7 d6 d5 d4 d3 d2 d1 d0 re-start register data byte a n r/w smbus device address byte (2ch) ack from ASC7621 nack from master stop by master register address pointer set (figure 2.) without stop by master + 1 9 1 9 smbus device address byte (2ch) ack from ASC7621 nack from master scl sda 1 9 1 9 stop by master d7 d6 d5 d4 d3 d2 d1 d0 start register data byte a n r/w figure 2 register address pointer set figure 3 register write figure 4 register read figure 5 register read when read address already set 0 1 1 1 0 s 0 0 1 1 1 0 s 0 0 1 1 1 0 s 0 0 1 1 1 0 s 0 0 0 0 preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 11 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 peci the ASC7621 is compatible with devices that are compliant with intel?s peci 1.0 specifications. more information on this interface may be found in their peci interface specifications. temperatures sent over the peci interface from the cpu are in celsius degrees relative to the thermal control circuit (tcc) temperature st ored internally in the cpu and accessed only through bios. this is the temperature limit where internal measures are taken to reduce power dissipation. fan speed control settings sent by the bios over the smbus to registers in the ASC7621 are made using this relative temperat ure rather than the absolute readings of remote or on-chip diodes. as many as four cpu clients on the peci bus are addressed in the range of 0x30 to 0x33. currently, each address is a single-packaged device that may have up to two domains or cpu-measured digital temperatures. general operation the peci host in ASC7621 performs the following functions: ? responds to smbus configuration identifying the presence of peci clients and the thermal zone associated with each client. ? reads the peci temperat ure of the domain(s) of each client processor addressed. ? stores the highest result from each peci address into temperature zone register associated to the measurement received from the client. (each address may be associated with any one temperature zone.) ? flags an error if no valid peci temperature can be read. ? continuously monitors the state of the peci interface for fault conditions. peci temperature format and range the peci temperatures read from the processor will be in the range 0 c to -127 c where 0 c is the hottest temperature and has the following format: temperature 2?s complement representation 0 c 0000 0000 00.00 0000 -1 c 1111 1111 11.00 0000 -5 c 1111 1110 11.00 0000 -32 c 1111 1000 00.00 0000 -127 c 1111 0000 01.00 0000 table 1 raw peci temperature format these readings are not accessible to the user but are filtered, re-formatted and assigned to a temperature zone. filtered peci temperature readings are accessible by the user before they are assigned to a temperature zone by reading registers f6h through fdh. these readings follow the format described in table 2. the peci temperatures assigned to a temperature zone are reported over smbus interface in temperature zone registers also will be in the range 0 c to -127 c. the format reported through temperature zone registers is re-aligned to agree with diode measurements. it is stored in two register locations in the following format with integer high byte and fractional low byte to be consistent with all other temperature reports: 2?s complement representation temperature high byte low byte 0 c 0000 0000 .0000 0000 -1 c 1111 1111 .0000 0000 -5 c 1111 1011 .0000 0000 -32 c 1110 0000 .0000 0000 -127 c 1000 0001 .0000 0000 table 2 peci temperature report format peci errors a specific set of temperature reading value encodings, well outside the operational range of 0 c to -127 c, are reserved to signal temperature sensor faults on the cpu to ASC7621 interface. these encodings are in the peci temperature format as delivered by the cpu and are converted to the appropriate interrupt status register 3 error bits described in the interrupt status register section below. preliminary specification ? s ubject to change without notice preliminary specific ation ? subject to change without notice - 12 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 register set register address r/w register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) de- fault value (hex) lock fan 3 zone # fan 2 zone # fan 1 zone # 00h r fan zone status 1 0 1 0 1 0 res res n/a zone 1 source zone 2 source 02h r/w zone 1 & 2 assignment res 2 1 0 res 2 1 0 00 x zone 3 source zone 4 source 03h r/w zone 3 & 4 assignment res 2 1 0 res 2 1 0 00 x 04h r/w tach 1 configuration 3-wire enable1 3-wire enable0 meas blank1 meas blank 0 meas dwell 1 meas dwell 0 meas duration 1 meas duration 0 36 x 05h r/w tach 2 configuration 3-wire enable1 3-wire enable0 meas blank1 meas blank 0 meas dwell 1 meas dwell 0 meas duration 1 meas duration 0 36 x 06h r/w tach 3 configuration 3-wire enable1 3-wire enable0 meas blank1 meas blank 0 meas dwell 1 meas dwell 0 meas duration 1 meas duration 0 36 x 07h r/w tach 4 configuration 3-wire enable1 3-wire enable0 meas blank1 meas blank 0 meas dwell 1 meas dwell 0 meas duration 1 meas duration 0 36 x 0eh r/w peci extended configuration four domain enable diode filter2 diode filter1 diode filter0 proc 3 enable proc 2 enable proc 1 enable proc 0 enable 21 x 10h r zone 1 temper- ature (ls byte) 1 0 x x x x x x n/a 11h r 3.3v (ls byte) 1 0 x x x x x x n/a 12h r 5v (ls byte) 1 0 x x x x x x n/a 13h r 2.5v (ls byte) 1 0 x x x x x x n/a 14h r 12v (ls byte) 1 0 x x x x x x n/a 15h r zone 2 temper- ature (ls byte) 1 0 x x x x x x n/a 16h r zone 3 temper- ature (ls byte) 1 0 x x x x x x n/a 17h r zone 4 temper- ature (ls byte) 1 0 x x x x x x n/a 18h r vccp (ls byte) 1 0 x x x x x x n/a alert assignment gpio 1 function 19h r/w gpio 1 configuration res res 1 0 gpio 1 bit 2 1 0 00 x gpio 2 function gpio 3 function 1ah r/w gpio 2 & 3 configuration gpio 2 bit 2 1 0 gpio 3 bit 2 1 0 00 x 1ch r/w remote 1 offset 7 6 5 4 3 2 1 0 00 x 1dh r/w remote 2 offset 7 6 5 4 3 2 1 0 00 x 20h r 2.5v (ms byte) 7 6 5 4 3 2 1 0 n/a 21h r vccp (ms byte) 7 6 5 4 3 2 1 0 n/a 22h r 3.3 v (ms byte) 7 6 5 4 3 2 1 0 n/a 23h r 5v (ms byte) 7 6 5 4 3 2 1 0 n/a 24h r 12v (ms byte) 7 6 5 4 3 2 1 0 n/a 25h r zone 1 temper- ature (ms byte) 9 8 7 6 5 4 3 2 n/a 26h r zone 2 temper- ature (ms byte) 9 8 7 6 5 4 3 2 n/a 27h r zone 3 temper- ature (ms byte) 9 8 7 6 5 4 3 2 n/a preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 13 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 register address r/w register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) de- fault value (hex) lock 28h r tach 1 ls byte 7 6 5 4 3 2 1 0 ff 29h r tach 1 ms byte 15 14 13 12 11 10 9 8 ff 2ah r tach 2 ls byte 7 6 5 4 3 2 1 0 ff 2bh r tach 2 ms byte 15 14 13 12 11 10 9 8 ff 2ch r tach 3 ls byte 7 6 5 4 3 2 1 0 ff 2dh r tach 3 ms byte 15 14 13 12 11 10 9 8 ff 2eh r tach 4 ls byte 7 6 5 4 3 2 1 0 ff 2fh r tach 4 ms byte 15 14 13 12 11 10 9 8 ff 30h r/w fan 1 current pwm duty 7 6 5 4 3 2 1 0 ff 31h r/w fan 2 current pwm duty 7 6 5 4 3 2 1 0 ff 32h r/w fan 3 current pwm duty 7 6 5 4 3 2 1 0 ff 33h r zone 4 temperature (ms byte) 9 8 7 6 5 4 3 2 n/a 34h r/w zone 4 low temp 7 6 5 4 3 2 1 0 81h 35h r/w zone 4 high temp 7 6 5 4 3 2 1 0 00h 36h r/w peci configuration res res res leg dom avg2 avg1 avg0 00h x 38h r/w fan 1 max duty cycle 7 6 5 4 3 2 1 0 ff x 39h r/w fan 2 max duty cycle 7 6 5 4 3 2 1 0 ff x 3ah r/w fan 3 max duty cycle 7 6 5 4 3 2 1 0 ff x 3bh r/w zone 4 fan temp limit 7 6 5 4 3 2 1 0 e0h x 3ch r/w zone 4 range, spike smoothing ran3 ran2 ran1 ran0 zn4e zn4-2 zn4-1 zn4-0 c3h x 3dh r/w zone 4 absolute temp limit 7 6 5 4 3 2 1 0 00h x 3eh r company id 7 6 5 4 3 2 1 0 61 3fh r version/ stepping ver3 ver2 ver1 ver0 4wire peci stp1 stp0 6c 40h r/w ready/lock/ start/override res res safe peci ovrid ready lock start 00 x 2 41h r interrupt status register 1 err zn3 zn2 zn1 5v 3.3v vccp 2.5v 00 42h r interrupt status register 2 err2 err1 fan4 fan3 fan2 fan1 err 12v 00 43h r interrupt status register 3 err res res res alovr comm data zn4 00h preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 14 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 register address r/w register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) de- fault value (hex) lock 44h r/w 2.5v low limit 7 6 5 4 3 2 1 0 00 45h r/w 2.5v high limit 7 6 5 4 3 2 1 0 ff 46h r/w vccp low limit 7 6 5 4 3 2 1 0 00 47h r/w vccp high limit 7 6 5 4 3 2 1 0 ff 48h r/w 3.3v low limit 7 6 5 4 3 2 1 0 00 49h r/w 3.3v high limit 7 6 5 4 3 2 1 0 ff 4ah r/w 5v low limit 7 6 5 4 3 2 1 0 00 4bh r/w 5v high limit 7 6 5 4 3 2 1 0 ff 4ch r/w 12v low limit 7 6 5 4 3 2 1 0 00 4dh r/w 12v high limit 7 6 5 4 3 2 1 0 ff 4eh r/w zone 1 low temperature 7 6 5 4 3 2 1 0 81 4fh r/w zone 1 high temperature 7 6 5 4 3 2 1 0 7f 50h r/w zone 2 low temperature 7 6 5 4 3 2 1 0 81 51h r/w zone 2 high temperature 7 6 5 4 3 2 1 0 7f 52h r/w zone 3 low temperature 7 6 5 4 3 2 1 0 81 53h r/w zone 3 high temperature 7 6 5 4 3 2 1 0 7f 54h r/w tach 1 minimum ls byte 7 6 5 4 3 2 1 0 ff 55h r/w tach 1 minimum ms byte 15 14 13 12 11 10 9 8 ff 56h r/w tach 2 minimum ls byte 7 6 5 4 3 2 1 0 ff 57h r/w tach 2 minimum ms byte 15 14 13 12 11 10 9 8 ff 58h r/w tach 3 minimum ls byte 7 6 5 4 3 2 1 0 ff 59h r/w tach 3 minimum ms byte 15 14 13 12 11 10 9 8 ff 5ah r/w tach 4 minimum ls byte 7 6 5 4 3 2 1 0 ff 5bh r/w tach 4 minimum ms byte 15 14 13 12 11 10 9 8 ff 5ch r/w fan 1 configuration zon2 zon1 zon0 inv alt spin2 spin1 spin0 62 x 5dh r/w fan 2 configuration zon2 zon1 zon0 inv alt spin2 spin1 spin0 62 x 5eh r/w fan 3 configuration zon2 zon1 zon0 inv alt spin2 spin1 spin0 62 x 5fh r/w zone 1 range/ fan 1 frequency ran3 ran2 ran1 ran0 hlfrq frq2 frq1 frq0 c3 x preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 15 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 register address r/w register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) de- fault value (hex) lock 60h r/w zone 2 range/ fan 2 frequency ran3 ran2 ran1 ran0 hlfrq frq2 frq1 frq0 c3 x 61h r/w zone 3 range/ fan 3 frequency ran3 ran2 ran1 ran0 hlfrq frq2 frq1 frq0 c3 x 62h r/w min/off, zone 1 spike smoothing off3 off2 off1 res zn1e zn1-2 zn1-1 zn1-0 00 x 63h r/w zone 2 / zone 3 spike smoothing zn2e zn2-2 zn2-1 zn2-0 zn3e zn3-2 zn3-1 zn3-0 00 x 64h r/w fan 1 pwm minimum 7 6 5 4 3 2 1 0 80 x 65h r/w fan 2 pwm minimum 7 6 5 4 3 2 1 0 80 x 66h r/w fan 3 pwm minimum 7 6 5 4 3 2 1 0 80 x 67h r/w zone 1 fan temp limit 7 6 5 4 3 2 1 0 5a x 68h r/w zone 2 fan temp limit 7 6 5 4 3 2 1 0 5a x 69h r/w zone 3 fan temp limit 7 6 5 4 3 2 1 0 5a x 6ah r/w zone 1 temp absolute limit 7 6 5 4 3 2 1 0 64 x 6bh r/w zone 2 temp absolute limit 7 6 5 4 3 2 1 0 64 x 6ch r/w zone 3 temp absolute limit 7 6 5 4 3 2 1 0 64 x 6dh r/w zone 1, zone 2 hysteresis h1-3 h1-2 h1-1 h1-0 h2-3 h2-2 h2-1 h2-0 44 x 6eh r/w zone 3, zone 4 hysteresis h3-3 h3-2 h3-1 h3-0 h4-3 h4-2 h4-1 h4-0 44 x 6fh r/w xor tree enable res res res res res res res xen 00 x 75h r/w fan spin-up mode tach4 disable tach3/4 disable tach2 disable tach1 disable res pwm3su pwm2su pwm1su 00 x notes: 1. reserved bits will always return 0 wh en read, x-bits in readings may be ignored. 2. when register 40h is locked, all bits are locked except 0 and 3 which remain user changeable. 3. two-byte or extended resolution temperature, voltage and ta chometer values are protected from changing when only one of the bytes is read. the implementation of a data word latch invo lves the register pairs in t he table below. when one of the address pairs is read, the mating data is latched at the same time. the next smbus access must be the mating address or the latch will be released. this implementation allows that the data may be read in the order of ls-ms or ms-ls and the pair will remain coherent. preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 16 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 ms-byte address (hex) ls-byte address (hex) data field name 25 10 zone 1 temperature 26 15 zone 2 temperature 27 16 zone 3 temperature 33 17 zone 4 temperature 20 13 2.5v 21 18 vccp 22 11 3.3v 23 12 5v 24 14 12v 29 28 tach 1 2b 2a tach 2 2d 2c tach 3 2f 2e tach 4 preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 17 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 temperature measurement diode temperatures are measured with a precision delta-v be methodology converted to a digital temperature reading by a 10-bit sigma-delta converter. peci interfac e to the cpu provide digital thermometer readings of substrat e temperature. the measurement system provides a means fo r assigning any of the temperature input s to a temperature zone. the user may set limits on these readings to be continuously monitored a nd alarm bits set when they are exceeded. separately, the measurements are also delivered to the automat ic fan control system to adjust fan sp eed. the following registers contain the readings from the internal and remote sensors. registers 25-10h, 26-15h and 27-0eh: temperature zone readings (10-bit, 2?s complement reporting) register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 25h r zone 1 temper- ature (ms byte) 9 8 7 6 5 4 3 2 n/a 10h r zone 1 temper- ature (ls byte) 1 0 x x x x x x n/a 26h r zone 2 temper- ature (ms byte) 9 8 7 6 5 4 3 2 n/a 15h r zone 2 temper- ature (ls byte) 1 0 x x x x x x n/a 27h r zone 3 temper- ature (ms byte) 9 8 7 6 5 4 3 2 n/a 16h r zone 3 temper- ature (ls byte) 1 0 x x x x x x n/a 33h r zone 4 temper- ature (ms byte) 9 8 7 6 5 4 3 2 n/a 17h r zone 4 temper- ature (ls byte) 1 0 x x x x x x n/a the temperature zone registers reflect t he current temperature of the internal and remote diodes or peci cpu digital thermometers. filtering is applied to all readings and this is described in the spike & smoothing filter section below. any temperature input may be assigned to any zone, according to the settings in the zone as signment registers, [02h] and [03h]. the default assignment is as follows: zone 1 temperature register r eports the temperature measured by the thermal diode connected to the remote 1- and remote 1+ pins if either: 1. peci monitoring is disabled (register [40h] bit 4=0) 2. peci monitoring is enabled but in legacy mode, (register [36h] bit 4, leg = 0). if peci monitoring is enabled (register [40h] bit 4=1) and legacy mode is leg = legacy mode (register [36h] bit 4, leg = 1), the register reports the highest digital thermometer reading by the processor. zone 2 temperature register reports the temperature measured by the inte rnal (junction) temperature sensor. zone 3 temperature register reports the te mperature measured by the thermal diode c onnected to the second set of remote 2- and remote 2+ pins. zone 4 reports temperatures as follows: 1. by default and if peci temperature is disabled (register [3 6h] bit 4, leg = 0) the zone 4 register is not used. in this case, special temperature value of 80h will be reported to in dicate that no temperature is available. if this zone is associated with any fan pwm controller(s), this will result in these controller(s) being overridden to 100% duty cycle. no error bits will be set in the interrupt status registers. 2. if peci monitoring is enabled [40h] bit 4=1) and legacy mode is in standard mode (register [36h] bit 4, leg = 0), the register will report the highest digital thermometer reading by the processor. 3. temperatures are represented as 10-bit, 2?s complemen t, signed numbers, in degrees celsius, as shown below in table 3. 4. if peci monitoring is enabled [40h] bit 4=1) and legacy mo de is in legacy mode (register [36h] bit 4, leg = 1), the register will report the temperature measured by the t hermal diode connected to the remote 1- and remote 1+ pins. preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 18 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 a remote diode temperature reading register will return a value of 8000h if the remote diode pins are not used by the board designer or is not functioning properly. this reading will ca use the zone limit bits (bits 4 and 6) in the interrupt status register (41h) and the remote diode fault st atus bit (bits 6 and 7) in the interrupt status register 2 (42h) to be set. these registers are read-only ? a write to these registers has no effect. digital output (2?s complement) high byte low byte temperature 10-bit resolution ignore +125 c 0111 1101 .00 xx xxxx +100 c 0110 0100 .00 xx xxxx +50 c 0011 0010 .00 xx xxxx +25 c 0001 1001 .00 xx xxxx +10 c 0000 1010 .00 xx xxxx +1.75 c 0000 0001 .11 xx xxxx +0.25 c 0000 0000 .01 xx xxxx 0 c 0000 0000 .00 xx xxxx -1.75 c 1111 1110 .01 xx xxxx -55 c 1100 1001 .00 xx xxxx table 3 relationship between temperature and 2?s complement digital output, -55c to +125c digital output (2?s complement) high byte low byte temperature 10-bit resolution ignore 0 c 0000 0000 .0000 00 xx -0.015625 c 1111 1111 .1111 11 xx -0.03125 c 1111 1111 .1111 10 xx -0.0625 c 1111 1111 .1111 00 xx -0.125 c 1111 1111 .1110 00 xx -0.25 c 1111 1111 .1100 00 xx -0.5 c 1111 1111 .1000 00 xx -1.0 c 1111 1111 .0000 00 xx -1.75 c 1111 1110 .0100 00 xx -2.0 c 1111 1110 0000 00 xx -25.0 c 1110 0111 0000 00 xx -100 c 1001 1100 0000 00 xx -127 c 1000 0001 0000 00 xx table 4 peci temperature format preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 19 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 temperature measurement configuration registers 02h and 03h: zone assignments register address r/w register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock zone 1 source zone 2 source 02h r/w zone 1 & 2 assignment res 6 5 4 res 2 1 0 00 x zone 3 source zone 4 source 03h r/w zone 3 & 4 assignment res 6 5 4 res 2 1 0 00 x the temperature measurement system has access to more temperature measuring device s than there are temperature zones that may be reported to the user or used to control a fan. it is allowed that any data input may be associated with any single temperature zone. however, if an attempt is made to assign a data source to more than one temperature zone report, the lowest order will be assigned and the other assignment will be ignored. do not attemp t to assign a data source to more than one temperature zone or multiple data sources to the same temperature zone. this register becomes read-only when the ready/lock/start/override register lock bit is set. any further attempts to write to this register shall have no effect. bit name zone 1 & 2 assignment [02h] value data source 000 internal temperature 001 remote 1 temperature 010 remote 2 temperature 011 internal temperature 100 peci processor temperature 0 101 peci processor temperature 1 110 peci processor temperature 2 2:0 zone 2 source 111 peci processor temperature 3 3 reserved reserved value data source leg = 0, remote 1 temperature 000 leg = 1, peci processor temperature 0 001 remote 1 temperature 010 remote 2 temperature 011 internal temperature 100 peci processor temperature 0 101 peci processor temperature 1 110 peci processor temperature 2 6:4 zone 1 source 111 peci processor temperature 3 7 reserved reserved table 5 zone 1 & 2 temperature reading assignment [02h] preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 20 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 bit name zone 3 & 4 assignment [03h] value data source leg = 0, peci processor temperature 0 000 leg = 1, remote 1 temperature 001 remote 1 temperature 010 remote 2 temperature 011 internal temperature 100 peci processor temperature 0 101 peci processor temperature 1 110 peci processor temperature 2 2:0 zone 4 source 111 peci processor temperature 3 3 reserved reserved value data source 000 remote 2 temperature 001 remote 1 temperature 010 remote 2 temperature 011 internal temperature 100 peci processor temperature 0 101 peci processor temperature 1 110 peci processor temperature 2 6:4 zone 3 source 111 peci processor temperature 3 7 reserved reserved table 6 zone 3 & 4 temperature reading assignment [03h] bit name default description 3:0 reserved 0 reserved 4 peci one- shot enable 0 0 = disable peci one shot, 1 = enable peci one-shot 5 reserved 0 reserved 6 run/stop 0 measurement system run(default) or stop (set to 1), places ASC7621 in a low-power or standby mode. 7 reserved 0 reserved table 7 configuration register [09h] bits preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 21 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 register 36h: peci configuration register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock 36h r/w peci configuration res res res leg dom avg2 avg1 avg0 00h x this register establishes legacy diode register assignment condition of temperature zo nes 1 and 4, leg; the number of domains per client, dom; and peci input filter coefficient s, avg[2:0]. this register becomes read-only when the ready/lock/start/override register lock bit is set. any further attempts to write to this register shall have no effect. bit field value function 000 (default) 0 sec. (no smoothing) 001 0.25 sec. 010 0.5 sec. 011 1.0 sec. 100 2.0 sec. 101 4.0 sec. 110 8.0 sec. 2:0 avg (peci input filter) 111 0 sec. 0 (default) processor contains a single domain (0) 3 dom 1 processor contains two domains (0,1) 0 (default) (standard mode) remote diode 1 reading is associated with temperature zone 1, peci is associated with zone 4 4 leg 1 (legacy mode) peci is associated with temperature zone 1, remote diode 1 is associated with zone 4 5:7 reserved 0 reserved table 8 peci configuration [36h] register 0eh: peci extended configuration register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock 0eh r/w peci extended configuration four domain enable diode filter2 diode filter1 diode filter0 proc 3 enable proc 2 enable proc 1 enable proc 0 enable 21 x this register establishes the number of domains per peci address and enables up to four peci clients to be polled for temperatures. if bit-0 through bit-3 are reset, peci will not be available. in addition, a remote diode noise filter may be tuned for opti mum performance when excessive noise is present in remote diode readings. this is a low-pass filter that also eliminates single sample spikes before they are stored in temperature zone registers. filter algorithm is descr ibed in the section on spike smoothing r egisters 62h, 63h and 3ch. times indicated in table 9 show the approximate filter response time to a step function in temperature diode measurement as applied to the assigned temperature zone reading. this register beco mes read-only when the ready/lock/ start/override register lock bit is set. any further attempts to write to this register shall have no effect. preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 22 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 bit field value function 0 peci processor 0 disabled 0 processor 0 enable 1 (default) peci processor 0 enabled 0 (default) peci processor 1 disabled 1 processor 1 enable 1 peci processor 1 enabled 0 (default) peci processor 2 disabled 2 processor 2 enable 1 peci processor 2 enabled 0 (default) peci processor 3 disabled 3 processor 3 enable 1 peci processor 3 enabled 000 0.25 sec. 001 1.1 sec. 010 (default) 2.4 sec. 011 3.4 sec. 100 5.0 sec. 101 6.8 sec. 110 10.2 sec. 6:4 diode filter 111 16.4 sec. 0 (default) 1 or 2 domains for enabled processors 7 four domain enable 1 3 or 4 domains for enabled processors table 9 peci extended configuration [0eh] register 1ch and 1dh: remote offset registers register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 1ch r/w remote 1 offset 7 6 5 4 3 2 1 0 00 1dh r/w remote 2 offset 7 6 5 4 3 2 1 0 00 this register provides a means to offset readings from remote diodes to compensate for errors due to system noise or series resistance. it may also be used to compensate for a di fference in temperature between the remote diode and the temperature of interest once that is characterized by the user. it is in 2?s co mplement format with 0.25 degree resolution. the range is -32 to +31.75 c and is described in table 10: offset temperature value[7:0] +31.75 c 0111 11.11 +31 c 0111 11.10 +1 c 0000 01.00 +0.5 c 0000 00.10 +0.25 c 0000 00.01 0 c 0000 00.00 -0.25 c 1111 11.11 -1 c 1111 11.00 -31 c 1000 01.00 -31.75 c 1000 00.01 -32 c 1000 00.00 table 10 offset temperature data format preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 23 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 voltage measurement and limits register 20-24h: voltage reading register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 20h r 2.5v (ms byte) 9 8 7 6 5 4 3 2 n/a 13h r 2.5v (ls byte) 1 0 x x x x x x n/a 21h r vccp (ms byte) 9 8 7 6 5 4 3 2 n/a 18h r vccp (ls byte) 1 0 x x x x x x n/a 22h r 3.3v (ms byte) 9 8 7 6 5 4 3 2 n/a 11h r 3.3v (ls byte) 1 0 x x x x x x n/a 23h r 5v (ms byte) 9 8 7 6 5 4 3 2 n/a 12h r 5v (ls byte) 1 0 x x x x x x n/a 24h r 12v (ms byte) 9 8 7 6 5 4 3 2 n/a 14h r 12v (ls byte) 1 0 x x x x x x n/a the register names define the typical input voltage at which t he reading is ? full scale or c000h. high byte readings are 8- bits with an ls bit value of nominal divided by 192 and 2-bi ts in the high-order portion of the ls byte having a value corresponding to ? and ? of that high byte ls bit value. ignore the lower 6-bits of the ls byte. the voltage reading registers are updated automatically by the ASC7621 at a minimum frequency of 4hz and a typical frequency of 5 hz. these registers are read onl y ? a write to these registers has no effect. register 44-4dh: voltage limit registers register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 44h r/w 2.5v low limit 7 6 5 4 3 2 1 0 00h 45h r/w 2.5v high limit 7 6 5 4 3 2 1 0 ffh 46h r/w vccp low limit 7 6 5 4 3 2 1 0 00h 47h r/w vccp high limit 7 6 5 4 3 2 1 0 ffh 48h r/w 3.3v low limit 7 6 5 4 3 2 1 0 00h 49h r/w 3.3v high limit 7 6 5 4 3 2 1 0 ffh 4ah r/w 5v low limit 7 6 5 4 3 2 1 0 00h 4bh r/w 5v high limit 7 6 5 4 3 2 1 0 ffh 4ch r/w 12v low limit 7 6 5 4 3 2 1 0 00h 4dh r/w 12v high limit 7 6 5 4 3 2 1 0 ffh if a voltage input either exceeds the value set in the voltage high limit register or falls below the value set in the voltage low limit register, the corresponding bit will be set automatically by the ASC7621 in the interrupt st atus registers (41-42h). the binary value of the voltage limits are extended to 16-bits and compared with the two-bytes of the voltage reading. voltages are presented in the registers at ? of fu ll-scale for the nominal voltage, meaning t hat at nominal voltage, each input will be c0h, as shown in table 11. note that 3.3v input is vdd and is not allowed to go be low 3.0v during normal operation. setting the ready/lock/start/ove rride register lock bit has no effect on these registers. input nominal voltage register reading at nominal voltage maximum voltage register reading at maximum voltage minimum voltage register reading at minimum voltage 2.5v 2.5v c0h 3.32v ffh 0v 00h vccp 2.25v c0h 3.00v ffh 0v 00h 3.3v 3.3v c0h 4.38v ffh 3.0v aeh 5v 5.0v c0h 6.64v ffh 0v 00h 12v 12.0v c0h 16.00v ffh 0v 00h table 11 voltage limits vs register setting (ms byte) preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 24 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 temperature measurement filtering filter architecture each temperature reading is carefully filt ered to remove spike transients and nois e generated by the com puter environment?s effect on sensitive analog measurements. filtering is t unable by the user and is applied in two general areas: 1. immediately after the measurem ent process before assigning a meas urement to a temperature zone. 2. after temperature zone assignment but before a fan is assigned to that temperature zone. an overview of this signal flow is in figure 6 below. figure 6 measurement filter block diagram spike & smoothing filter algorithm the spike & smoothing filter algorithm has two phases of filtering. first, a ?no-spik e? value is created from the current and three previous values. the result is an average of the two remaining values when the high and low values are removed. the second phase is a user specified filt er and coefficient. this filter determines a smoothed temperature value, smooth t i , by taking the no-spike t i , subtracting the previous sm oothed temperature, smooth t i-1 , divided by 2 n and adding that to the previously smoothed temperature. n and gain are coefficients se lected internally to provide the spike filter smoothing time constants (step input response time) shown in table 8, table 9 and table 23. for the current temperature reading t i : no-spike t i = (discard min and max of (t i , t i-1 , t i-2 , t i-3 ))/2 smooth t i = gain * (no-spike t i - smooth t i-1 )/2 n + smooth t i-1 status registers register 41h: interrupt status register 1 register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 41h r interrupt status 1 err zn3 zn2 zn1 5v 3.3v vccp 2.5v n/a the interrupt status register 1 bits will be automatically set, by the ASC7621, whenever a fault condition is detected. a faul t condition is detected whenever a measured value is outside the window set by its limit registers. zn1 bit will be set when a diode fault condition, such as an open or short, is detected. more than one fault may be indicated in the interrupt register when read. the register will hold set bit(s) until the event is read by software. the contents of this register will be clear ed (set to 0) automatically by the ASC7621 after it is read by so ftware, if the fault condition no longer exists. once set, the interrupt status register 1 bits will remain set until a read event occurs, even if the fault condition no longer exists. this register is read-only ? a write to this register has no effect. - converte r peci input spike & smoothing filter (user tuned) spike & smoothing filter (user tuned) up to 7 temperature inputs into 4 temperature zone assignments and limit evaluations 4 zone to 3 fan pwm assignments spike & smoothing filter (user tuned) fan speed control two remote diodes and internal diode up to 4 peci addresses select maximum from each peci address tuning: register 36h bits 2:0, table 8 tuning: register 0eh bits 6:4, table 9 tuning: register 62h bits 3:0, register 63h bits 7:4 and 3:0, register 3ch bits 3:0, table 23 temperature zone 1-4 reports filtered peci reports preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 25 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 bit name r/w default description 0 2.5v limits exceeded r 0 the ASC7621 automatically sets this bit to 1 when the 2.5v input voltage is less than or equal to the limit set in the 2.5v low limit register or greater than the limit set in the 2.5v high limit register. 1 vccp limits exceeded r 0 the ASC7621 automatically sets this bit to 1 when the vccp input voltage is less than or equal to the limit set in t he vccp low limit register or greater than the limit set in the vccp high limit register. 2 3.3v limits exceeded r 0 the ASC7621 automatically sets this bit to 1 when the 3.3v input voltage is less than or equal to the limit set in the 3.3v low limit register or greater than the limit set in the 3.3v high limit register. 3 5v limits exceeded r 0 the ASC7621 automatically sets this bit to 1 when the 5v input voltage is less than or equal to the limit set in the 5v low limit register or greater than the limit set in the 5v high limit register. 4 zone 1 limit exceeded r 0 the ASC7621 automatically sets this bit to 1 when the temperature input measured by the remote1- and remote1+ inputs is less than or equal to the limit set in the processor (zone 1) low temp register or more than the limit set in the processor (zone 1) high temp register. this bit will be set when a diode fault is detected. 5 zone 2 limit exceeded r 0 the ASC7621 automatically sets this bit to 1 when the temperature input measured by the internal temperature s ensor is less than or equal to the limit set in the thermal (zone 2) low temp register or greater than the limit set in the internal (zone 2) high temp register. 6 zone 3 limit exceeded r 0 the ASC7621 automatically sets this bit to 1 when the temperature input measured by the second remote temperature sensor is less than or equal to the limit set in the thermal (zone 3) low temp register or greater than the limit set in the internal (zone 3) high temp register. 7 error in status register 2 r 0 if there is a set bit in status register 2, this bit will be set to 1. table 12 interrupt status register 1 register 42h: interrupt status register 2 register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 42h r interrupt status 2 err2 err1 fan4 fan3 fan2 fan1 err 12v n/a the interrupt status register 2 bits will be automatically se t, by the ASC7621, whenever a fault condition is detected. interrupt status register 2 identifies faults caused by temper ature sensor error, fan speed dropping below minimum set by the tachometer minimum register. interrupt status register 2 will hold a set bit until the event is read by software. the contents of this register will be cleared (set to 0) automatically by the ASC7621 afte r it is read by software, if fault condit ion no longer exists. once set, the interrupt status register 2 bi ts will remain set until a read event occurs, even if the fault no longer exists. this register is read-only ? a write to this register has no effect. bit name r/w default description 0 12v limits exceeded r 0 the ASC7621 automatically sets this bit to 1 when the 12v input voltage is less than or equal to the limit set in the 12v low limit register or greater than the limit set in the 12v high limit register. 1 error in status register 3 r 0 if there is a set bit in status register 3, this bit will be set to 1 2 fan 1 stalled r 0 the ASC7621 automatically sets this bi t to 1 when the tach 1 input reading is above the count value set in the tach 1 minimum msb and lsb registers. 3 fan 2 stalled r 0 the ASC7621 automatically sets this bi t to 1 when the tach 2 input reading is above the count value set in the tach 2 minimum msb and lsb registers. 4 fan 3 stalled r 0 the ASC7621 automatically sets this bi t to 1 when the tach 3 input reading is above the count value set in the tach 3 minimum msb and lsb registers. 5 fan 4 stalled r 0 the ASC7621 automatically sets this bi t to 1 when the tach 4 input reading is above the count value set in the tach 4 minimum msb and lsb registers. preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 26 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 bit name r/w default description 6 remote diode 1 fault r 0 the ASC7621 automatically sets this bit to 1 when there is an open circuit fault on the remote1+ or remote1- thermal diode input pins. a diode fault will also set bit 4 zone 1 limit bit, of interrupt status register 1. 7 remote diode 2 fault r 0 the ASC7621 automatically sets this bit to 1 when there is an open circuit fault on the remote2+ or remote2- thermal diode input pins. a diode fault will also set bit 6 zone 3 limit bit, of interrupt status register 1. table 13 interrupt status register 2 register 43h: interrupt status register 3 register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 43h r interrupt status 3 res res res res alovr comm data zn4 n/a the interrupt status register 3 bits will be automatically se t, by the ASC7621, whenever a fault condition is detected. interrupt status register 3 identifies faults caused by temperature zone exceeding absolute limits, peci communication error, peci data error and zone 4 temperature limit exceeded. in terrupt status register 3 will hold a set bit until the event is read by software. the contents of this register will be clear ed (set to 0) automatically by the ASC7621 after it is read by software, if fault condition no longer exists. once set, the in terrupt status register 3 bits will remain set until a read eve nt occurs, even if the fault no longer exists. this register is read only ? a write to this register has no effect. bit name r/w default description 0 zn4 r 0 the ASC7621 automatically sets this bit to 1 when the zone 4 limit is exceeded. 1 data r 0 the ASC7621 sets this bit when any of the peci processor status reports peci error = 1 and peci underflow = 1, this indicates a data error occurred with a peci processor. 2 comm r 0 the ASC7621 automatically sets this bit to 1 when any of the peci processor status reports peci error = 1 and peci underflow = 0 this indicates a communications error occurred with a peci processor. 3 alovr r 0 the ASC7621 automatically sets this bit to 1 when any temperature zone exceeds its absolute temperature limit. 4 reserved r 0 reserved. 5 reserved r 0 reserved. 6 reserved r 0 reserved. 7 reserved r 0 reserved. table 14 interrupt status register 3 tachometer measurement and configuration register 28-2fh: fan tachometer reading register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 28h 29h r r tach 1 ls byte tach 1 ms byte 7 15 6 14 5 13 4 12 3 11 2 10 1 9 0 8 n/a n/a 2ah 2bh r r tach 2 ls byte tach 2 ms byte 7 15 6 14 5 13 4 12 3 11 2 10 1 9 0 8 n/a n/a 2ch 2dh r r tach 3 ls byte tach 3 ms byte 7 15 6 14 5 13 4 12 3 11 2 10 1 9 0 8 n/a n/a 2eh 2fh r r tach 4 ls byte tach 4 ms byte 7 15 6 14 5 13 4 12 3 11 2 10 1 9 0 8 n/a n/a the fan tachometer reading register s contains the number of 11.111 s periods (90 khz) between full fan revolutions. the results are based on the time interval of two tachometer pul ses, since most fans produce two tachometer pulses per full preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 27 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 revolution. these registers will be updated at least once every second. common interpretation of tachometer readings is to take the binary period measurement and convert it to rpm. this may be done by applying the formula: rpm = (90,000 x 60)/(decimal equivalent of binary tach reading) the value, for each fan, is repres ented by a 16-bit unsigned number. the fan tachometer reading registers will always return an accurate fan tachometer measurement, even when a fan is disabled or non-functional, however, if pwm commands for a fan (register 30h to 32h) is zero, tach measurements are suspended and the last reading may remain in the register. in the case of a three-wire fan being driven by pwm signal connected to fan power, the pw m output is held high for the period of the tachometer measurement. this stretching of t he pwm will result in an exaggeration of the pwm command at low rpm. these registers are read-only ? a write to these registers has no effect. when the ls byte of the ASC7621 16-bit regist er is read, the other byte (ms byte) is latched at the current value until it is read. at the end of the ms byte read the fan tachometer reading registers ar e updated. during spin-up, the pwm duty cycle reported is 0%. registers 54-5bh: fan tachometer limits register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 54h r/w tach 1 minimum ls byte 7 6 5 4 3 2 1 0 ff 55h r/w tach 1 minimum ms byte 15 14 13 12 11 10 9 8 ff 56h r/w tach 2 minimum ls byte 7 6 5 4 3 2 1 0 ff 57h r/w tach 2 minimum ms byte 15 14 13 12 11 10 9 8 ff 58h r/w tach 3 minimum ls byte 7 6 5 4 3 2 1 0 ff 59h r/w tach 3 minimum ms byte 15 14 13 12 11 10 9 8 ff 5ah r/w tach 4 minimum ls byte 7 6 5 4 3 2 1 0 ff 5bh r/w tach 4 minimum ms byte 15 14 13 12 11 10 9 8 ff the fan tachometer low limit registers indicate the tachomet er reading under which the corresponding bit will be set in the interrupt status register 2 register. in auto fan control m ode, the fan can run at low speeds, so care should be taken in software to ensure that the limit is high enough not to cause sporadic alerts. the fan tachometer will not cause a bit to be set in interrupt status register 2 if t he current value in current pwm duty registers (30h to 32h) is 00h or if the fan is disabled via the fan configuration register. interrupts will not be generated for a fan if its minimum is set to ff ffh except for timeout. setting the ready/lock/st art/override register lock bit has no effect on these registers. given the relative insignificance of bit 0 and bit 1, these bits could be programmed to designate the physical location of the fan generating the tachometer signal, as follows: register name bit 1 bit 0 (lsb) cpu cooler 0 0 memory controller 0 1 chassis front 1 0 chassis rear 1 1 preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 28 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 register 04-07h: fan tachometer measurement configuration register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock 04h r/w tach 1 configuration 3-wire enable 1 3-wire enable 0 meas blank 1 meas blank 0 meas dwell 1 meas dwell 0 meas duration 1 meas duration 0 36 x 05h r/w tach 2 configuration 3-wire enable 1 3-wire enable 0 meas blank 1 meas blank 0 meas dwell 1 meas dwell 0 meas duration 1 meas duration 0 36 x 06h r/w tach 3 configuration 3-wire enable 1 3-wire enable 0 meas blank 1 meas blank 0 meas dwell 1 meas dwell 0 meas duration 1 meas duration 0 36 x 07h r/w tach 4 configuration 3-wire enable 1 3-wire enable 0 meas blank 1 meas blank 0 meas dwell 1 meas dwell 0 meas duration 1 meas duration 0 36 x the fan tachometer configurati on registers contain the settings that define the modes of measurement of the tachometer input signals. the user is allowed to disable a tachometer measurement or to request pwm st retching, in the case of a 3- wire fan. also, the rate, start-up and period of measurements within a fan rotation cycle may be selected. the table below describes the controls. this register becomes read-only when the ready/lock/start/override register lock bit is set. any further attempts to write to this register shall have no effect. bit name r/w default description 1:0 measurement duration r/w 10 the amount of fan rotation used for the tach measurement. assumes 2 pulse periods per rotation of fan. 00: ? rotation ? tach count x4 = reported value 01: ? rotation ? tach count x2 = reported value 10: 1 rotation ? tach count x1 = reported value (default) 11: 2 rotation ? tach count x1 = reported value 3:2 measurement dwell r/w 01 delay between tach measurements 00: 100 ms 01: 300 ms (default) 10: 500 ms 11: 728 ms 5:4 measurement blank r/w 11 in 3-wire fan mode, a delay is needed to assure that the tach input has stabilized after the pwm has been set to 100% 00: 11.1 s 01: 22.2 s 10: 33.3 s 11: 44.4 s (default) 7:6 3-wire enable r/w 00 for 3-wire mode, the pwm output will be forced to 100% when the tach measurement is being processed. each fan has a 3- wire mode control that will behave as indicated in this table: hlfrq (5fh-61h) 3-wire enable (7:6) 3-wire mode 0 0 0 enabled 0 0 1 enabled 0 1 0 enabled 0 1 1 disabled 1 0 0 disabled 1 0 1 disabled 1 1 0 enabled 1 1 1 disabled table 15 tachometer configuration register preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 29 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 automatic fan control auto fan control operating mode the ASC7621 includes the circuitry for automatic fan control. in auto fan mode, the asc76 21 will automatically adjust the pwm duty cycle of the pwm output. pwm outputs are assigned to a thermal zone based on the fan configuration registers. at any time, the temperature of a zone exceeds its absolute limit, all pwm outputs will go to 100% duty cycle to provide maximum cooling to the system. figure 7 automatic fan speed control example example for pwm1 assigned to zone 1: ? zone 1 fan temp limit (register 67h) is set to 50 c (32h). ? zone 1 range (register 5fh) is set to 8 c (6xh). ? fan pwm minimum (register 64h) is set to 50% (80h). in this case, the pwm duty cycle will be 50% at 50 c. since (zone 1 fan temp limit) + (zone 1 range) = 50 c + 8 c = 58 c, the fan will run at 100% duty cycle when the temperature of the z one 1 sensor reaches 58 c. since the midpoint of t he fan control range is 54 c, and the median duty cycle is 75% (halfway between the pwm minimum and 100%), pwm1 duty cycle would be 75% at 54 c. above (zone 1 fan temp limit) + (zone 1 range), the duty cycle will be 100%. 5 c hysteresis temperature c pwm set to off or minimum below this temperature pwm 100% fan temp limit less hysteresis fan temp limit hysteresis (0 c to 15 c) range (2 c to 80 c) fan temp limit plus range absolute limit p w m d u t y c y c l e l i n e a r l y i n c r e a s i n g w i t h t e m p p w m du t y c y c l e l i n e a r l y d e c r e a s i n g w i t h t e m p pwm set to off example 45 58 80 min% 100% pwm % minimum pwm set to 50%, fan speed increases linearly beyond 50 c but will not return to off until it has gone below fan temp limit by the 5 c hysteresis setting to 45c. temperature pwm % linear control range 8 c range off/ min% pwm set to minimum 100% 0% 50 user choice: set to minimum or off 5 c hysteresis temperature c pwm set to off or minimum below this temperature pwm 100% fan temp limit less hysteresis fan temp limit hysteresis (0 c to 15 c) range (2 c to 80 c) fan temp limit plus range absolute limit p w m d u t y c y c l e l i n e a r l y i n c r e a s i n g w i t h t e m p p w m du t y c y c l e l i n e a r l y d e c r e a s i n g w i t h t e m p pwm set to off example 45 58 80 min% 100% pwm % minimum pwm set to 50%, fan speed increases linearly beyond 50 c but will not return to off until it has gone below fan temp limit by the 5 c hysteresis setting to 45c. temperature pwm % linear control range 8 c range off/ min% pwm set to minimum 100% 0% 50 user choice: set to minimum or off preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 30 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 automatic fan speed control using maximum pwm setting the previously described and illustrated mode had no restrict ion on the maximum pwm setting. it is useful to limit the maximum pwm command sent to the fan in order to minimize the acoustic impact. the maximum pwm setting will clamp the automatic fan pwm command at a user selected value. the absolute limit setting will still cause the pwm command to be 100% and that will remain until the te mperature falls below the absolute limi t temperature by an amount equal to the hysteresis setting. this will minimize the acoustic impac t of having a temperature moving back and forth close to the absolute limit. the absolute limit may be set above or below the fan temp limit plus range. the pwm value will be overridden and will follow the hysteresis curve in either case, but the acoustic im pact will be different, running the fan to 100% pwm at a lower temperature, but enhancing the cooling effect. ab solute limit set on the low end is shown in figure 8 figure 7. setting it above is shown in figure 9. it is important to consider the combi nation of fan temp limit, range, maximum pwm and absolute limit and their impact on cooling and acoustics. in addition, the capability to operat e a fan from a combination of thermal zones allows a compound linear slope to be achieved for further optimization. figure 8 fan control with absolute limit set below fan temp limit plus range pwm set to off pwm 100% fan temp limit less hysteresis fan temp limit hysteresis (0 c to 15 c) range (2 c to 80 c) fan temp limit plus range absolute limit p w m d u t y c y c l e l i n e a r l y i n c r e a s i n g w i t h t e m p p w m d u t y c y c l e l i n e a r l y d e c r e a s i n g w i t h t e m p fan set to off temperature fan speed linear control range fan set to minimum hysteresis (0 c to 15 c) maximum pwm % pwm set to off pwm 100% fan temp limit less hysteresis fan temp limit hysteresis (0 c to 15 c) range (2 c to 80 c) fan temp limit plus range absolute limit p w m d u t y c y c l e l i n e a r l y i n c r e a s i n g w i t h t e m p p w m d u t y c y c l e l i n e a r l y d e c r e a s i n g w i t h t e m p fan set to off temperature fan speed linear control range fan set to minimum hysteresis (0 c to 15 c) maximum pwm % preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 31 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 figure 9 fan control with absolute limit set above fan temp limit plus range figure 10 automatic fan control algorithm begin fan spin up set fan output to 100% end polling cycle begin polling cycle fan output at 0%? fan spinning up? set fan output to auto fan mode minimum speed set fan output to 0% temp >= abslimit? temp >= limit? fan output at 0%? off / min set to 1? below hysteresis? override pwm output to 100% set fan speed based on auto fan range algorithm auto fan mode initiated yes yes (minimum speed) yes yes yes yes yes no no no no no no no no (off) yes min speed or spin-up time met? end fan spin up pwm= 100%? yes no below hysteresis? yes no pwm= preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 33 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 hlfrq frq [2:0] pwm frequency 0 000 ~10 hz 0 001 ~15 hz 0 010 ~23 hz 0 011 ~30 hz (default) 0 100 ~38 hz 0 101 ~47 hz 0 110 ~62 hz 0 111 ~94 hz 1 000 ~23 khz 1 001 ~24 khz 1 010 ~25 khz 1 011 ~26 khz 1 100 ~27 khz 1 101 ~28 khz 1 110 ~29 khz 1 111 ~30 khz table 16 register setting vs pwm frequency ran[3:0] linear control range ( c) 0000 2 0001 2.5 0010 3.33 0011 4 0100 5 0101 6.67 0110 8 0111 10 1000 13.33 1001 16 1010 20 1011 26.67 1100 32 (default) 1101 40 1110 53.33 1111 80 table 17 zone range setting, ran[3:0] this register becomes read-only when the ready/lock/start/overri de register lock bit is set. an y further attempts to write to this register shall have no effect. after power up t he default value is used for bits 3:0 of registers 5f-61h whenever the ready/lock/start/override register start bit is cleared ev en though modifications to this register are possible. preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 34 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 register 40h: ready/lock/start/override register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 40h r/w ready/lock/start/ override res res safe peci ovrid ready lock start 00 bit name r/w default description 0 start r/w 0 when software writes a 1 to this bi t, the ASC7621 fan monitoring and pwm output control functions will use the va lues set in the fan control limit and parameter registers (addresses 30-32h and 5fh through 61h). before this bit is set, the ASC7621 will not update the used register values, the default values will remain in effect. whenever this bi t is set to 0, the ASC7621 fan monitoring and pwm output control functions use the default fan limits and parameters, regardless of the current values in the limit and parameter registers (addresses 30-32h and 5fh through 61h) . the ASC7621 will preserve the values currently stored in the limit and par ameter registers when this bit set or cleared. this bit is not affected by the state of the lock bit. it is expected that all limit and parameter registers will be set by bios or application software prior to setting this bit. 1 lock r/w 0 setting this bit to 1 locks specified limit and parameter registers. warning: once this bit is set, limit and parameter registers become read-only and will remain locked until the device is powered off . this register bit becomes read-only once it is set. 2 ready r 0 the ASC7621 sets this bit automatically after the part is fully powered up, has completed the power-up-reset process, and after all a/d converters are properly functioning. 3 ovrid r/w 0 if this bit is set to 1, all pwm output s will go to 100% duty cycle regardless of whether or not the lock bit is set. the ovrid bit has precedence over the disabled mode. therefore, when ovrid is set the pwm will go to 100% even if the pwm is in the disabled mode. 4 peci r/w 0 when software writes a 1 to this bit, support for the monitoring of processor temperatures via the peci interface is enabled. this bit becomes read only when the lock bit is set to 1. 5 safe r/w 0 when software writes a 1 to this bit, it indicates that when operating the fan in manual mode, the pwm duty cycle will be overridden to 100% when any zone exceeds its absolute limit. when the bit is set to 0, it indicates that when operating the fan in manual mode, the pwm duty cycle will not be overridden to 100% when any zone exceeds its absolute limit. 6-7 reserved r 0 reserved table 18 ready / lock / start / ovrid settings register 30-32h: current pwm duty cycle register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 30h r/w fan 1 current pwm duty 7 6 5 4 3 2 1 0 ff 31h r/w fan 2 current pwm duty 7 6 5 4 3 2 1 0 ff 32h r/w fan 3 current pwm duty 7 6 5 4 3 2 1 0 ff the current pwm duty registers store t he current duty cycle at each pwm output. at initial power-on, the pwm duty cycle is 100% and thus, when read, this register will return ffh. a fter the ready/lock/start/override r egister start bit is set, thi s register and the pwm signals will be updated based on the algor ithm described in the auto fan control operating mode section. when ready/lock/start/ove rride register start bit is zero , default value (ffh) is used. preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 35 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 when read, the current pwm duty registers return the current pwm duty cycle. these registers are read-only unless the fan is in manual (test) mode, in which case a write to these registers will directly control the pwm duty cycle for each fan. the pwm duty cycle is represented as shown in table 19. if a 3-wire fan is being used and the option to enable 3-wire ta ch measurement is selected, the effective pwm duty cycle will be impacted by this feature. the 3-wire enable setting will hold the pwm signal high for the period taken to make a tachometer reading. this period depends on the rpm and various tachometer meas urement parameters. overall impact is that lower pwm commands will be effectively increased and there may be acoustic effects. register value current pwm % binary hex 0% 0000 0000 00 ~25% 0100 0000 40 ~50% (default) 1000 0000 80 ~75% 1100 0000 c0 100% 1111 1111 ff table 19 current pwm duty cycle setting register 4e-53h and 39h-3ah: temperature zone limit registers register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 4eh r/w zone 1 low temperature 7 6 5 4 3 2 1 0 81 4fh r/w zone 1 high temperature 7 6 5 4 3 2 1 0 7f 50h r/w zone 2 low temperature 7 6 5 4 3 2 1 0 81 51h r/w zone 2 high temperature 7 6 5 4 3 2 1 0 7f 52h r/w zone 3 low temperature 7 6 5 4 3 2 1 0 81 53h r/w zone 3 high temperature 7 6 5 4 3 2 1 0 7f 34h r/w zone 4 low temperature 7 6 5 4 3 2 1 0 81 3ah r/w zone 4 high temperature 7 6 5 4 3 2 1 0 00 if an external temperature input or the internal temperature sensor either exceeds the value set in the corresponding high limit register or falls below the value set in the corresponding low limit register, the corresponding bit will be set automati cally by the ASC7621 in the interrupt status register 1 (41h). for example, if the temperatur e read from the remote - and remote + inputs exceeds the zone 1 high temp register limit setting, interrupt status register 1 zn1 bit will be set. the temperature limits in these registers ar e represented as 8 bit 2?s complement, signed numbers in celsius, as shown below in table 20. setting the ready/lock/st art/override register lock bit has no effect on these registers. preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 36 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 temperature temperature limit (2?s complement) >127 c 0111 1111 +127 c (default high) 0111 1111 +125 c 0111 1101 +90 c 0101 1010 +50 c 0011 0010 +25 c 0001 1001 0 c 0000 0000 -50 c 1100 1110 -127 c (default low) 1000 0001 table 20 temperature zone high- and low-limit registers - 8-bit two?s complement register 5c-5eh: fan temperature zone assignment and spin-up mode register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock 5ch r/w fan 1 configuration zon2 zon1 zon0 inv alt spin2 spin1 spin0 62 x 5dh r/w fan 2 configuration zon2 zon1 zon0 inv alt spin2 spin1 spin0 62 x 5eh r/w fan 3 configuration zon2 zon1 zon0 inv alt spin2 spin1 spin0 62 x this register becomes read-only when the ready/lock/start/override register lock bit is set. any further attempts to write to this register shall have no effect. bits [7:5] zone/mode and bit [3] alternate zone/mode bits [7:5] of the fan configuration registers associate each fan with a temperature zone. when in auto fan mode the fan will be assigned to a zone, and its pwm duty cycle will be adjust ed according to the temperature of that zone. if ?hottest? option is selected (110), the fan will be c ontrolled by the the hottest of zones 1, 2 or 3. to determine the ?hottest zone?, t he pwm level for each zone is calculated then the zone with the hi gher pwm value (not temperature) is selected. when in manual control mode, the current pwm duty register (30-32h) become read/write. it is then possible to control the pwm outputs with software by writing to these registers. when t he fan is disabled (100) the corresponding pwm output should be driven low (or high, if inverted). bit-3 enables an alternate set of definitions for the zon[2:0] zone/mode bits described in table 21. fan configuration alt = 0 zon [2:0] fan configuration alt = 1 zon[2:0] fan on zone 1. 000 fan on zone 4. 000 fan on zone 2. 001 fan controlled by hottest of zones 1, 2, 3, and 4. 001 fan on zone 3. 010 reserved. (fan on full. pwm = 255.) 010 fan on full. pwm = 255. 011 reserved. (fan on full. pwm = 255.) 011 fan disabled. pwm = 0. 100 vendor specific. (fan on full. pwm = 255.) 100 fan controlled by hottest of 2, or 3. 101 vendor specific. (fan on full. pwm = 255.) 101 fan controlled by hottest of zones 1, 2, and 3. 110 vendor specific. (fan on full. pwm = 255.) 110 fan manually controlled (test mode) 111 vendor specific. (fan on full. pwm = 255.) 111 table 21 fan zone setting bit [4] pwm invert bit [4] inverts the pwm output. if set to 0, 100% duty cycle will yield an output that is always high. if set to 1, 100% duty cycle will yield an output that is always low. bit [2:0] spin up bits [2:0] specify the ?spin up? time for the fan. when a fan is being started from a stationary st ate, the pwm output is held at 100% duty cycle for the time specified in the table below before scaling to a lower speed. preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 37 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 spin up time spin[2:0] 0 ms 000 100 ms 001 250 ms 010 400 ms 011 700 ms 100 1000 ms 101 2000 ms 110 4000 ms 111 table 22 fan spin-up register register 00h: zone status register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock fan 3 zone # fan 2 zone # fan 1 zone # 00h r fan zone status 1 0 1 0 1 0 res res n/a the fan zone status register r eports the current temperature zone assignment to a fan. it reveals the actual assignment when the user has selected a mode in whic h the hottest of multiple zones to det ermine fan speed. zone 1 = 01b, zone 2 = 10b, zone 3 = 11b and zone 4 = 00b. if a fixed assignment or m anual fan speed control is used these zone #s will return 00b. this is a read-only register, a write has no effect. register 62h, 63h, 3ch: min/off, spike smoothing register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock 62h r/w min/off, zone1 spike smoothing off3 off2 off1 res zn1e zn1-2 zn1-1 zn1-0 00 x 63h r/w zone2 spike smoothing zn2e zn2-2 zn2-1 zn2-0 zn3e zn3-2 zn3-1 zn3-0 00 x 3ch r/w zone 4 range, spike smoothing ran3 ran2 ran1 ran0 zn4e zn4-2 zn4-1 zn4-0 c3h x the off1-off3 (bits 7 to 5) specify whether the duty cy cle will be 0% or minimum fan duty when the measured temperature falls below the temper ature limit register setting (see table 24 below). if the remote pins are connected to a processor or chipse t, instantaneous temperature spikes may be sampled by the ASC7621. temperature readings are first passed through a us er-programmable filter describ ed above in the temperature measurement filter section a nd then assigned to a temperatur e zone for fan speed control. if these spikes are not filtered, the cpu fan (if connected to ASC7621) may tu rn on prematurely or produce unpleasant noise. for this reason, any zone that is connected to a ch ipset or processor should have spike smoothing enabled. individual system characteristics will determine how large this coefficient should be. when spike smoothing is enabled, t he temperature reading registers will contain a va lue that is the result of the first filter. a second filter acts on the assigned temperature zone and is ?smoothed out ? for fan speed control. table 23 shows the approximate filter response time to a st ep function in temperature zone reading. zn1e, zn2e, zn3e and zn4e enable temperature smoothing for zones 1, 2, 3 and 4 respectively. zn1-2, zn1-1 and zn1-0 control smoothing time for zone 1. zn2-2, zn2-1 and zn2-0 control smoothing time for zone 2. zn3-2, zn3-1 and zn3-0 control smoothing time for zone 3. zn4-2, zn4-1 and zn4-0 control smoothing time for zone 4. these registers become read-only when the ready/lock/start/ov erride register lock bit is set. any further attempts to write to these registers shall have no effect. preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 38 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 0 10 20 30 40 50 60 123456789101112 figure 11 representation of what temperature is passed to the ASC7621 auto fan control with (green) and without (red dashed) spike smoothing spike smoothing time znn-[2:0] 35 seconds 000 17.6 seconds 001 11.8 seconds 010 7.0 seconds 011 4.4 seconds 100 3.0 seconds 101 1.6 seconds 110 0.8 seconds 111 table 23 spike smoothing for zn1 to zn4 pwm action off/min bit at 0% duty below limit 0 at min pwm duty below limit 1 table 24 pwm output below limit depending on value of off/min register 64-66h: minimum pwm duty cycle register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock 64h r/w fan 1 pwm minimum 7 6 5 4 3 2 1 0 80 x 65h r/w fan 2 pwm minimum 7 6 5 4 3 2 1 0 80 x 66h r/w fan 3 pwm minimum 7 6 5 4 3 2 1 0 80 x this register specifies the minimum duty cycle that t he pwm will output when the meas ured temperature reaches the temperature limit register setting. this register becomes read-only when the ready/lock/start/override register lock bi t is set. any further attempts to write to this register shall have no effect. preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 39 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 register value minimum pwm % binary hex 0% 0000 0000 00 ~25% 0100 0000 40 ~50% (default) 1000 0000 80 ~75% 1100 0000 c0 100% 1111 1111 ff table 25 minimum pwm duty cycle setting register 38-3ah: maximum pwm duty cycle register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock 38h r/w fan 1 max duty cycle 7 6 5 4 3 2 1 0 ff x 39h r/w fan 2 max duty cycle 7 6 5 4 3 2 1 0 ff x 3ah r/w fan 3 max duty cycle 7 6 5 4 3 2 1 0 ff x the maximum pwm duty registers store the maximum duty cycle that may be commanded at each pwm output under automatic fan control. this va lue is overridden to 100% when the assigned zone?s temperature has exceeded the absolute maximum temperature setting. when temperature falls below absolute maximum, pwm comma nd will resume the linear ramp only after it has fallen by the thermal zone hysteresis value (registers 6d-6eh). values follow the representation in table 19. this register becomes read-only when the ready/lock/start/override register lock bit is set. any further attempts to write to this register shall have no effect. register 67-69h: temperature limit register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock 67h r/w zone 1 fan temp limit 7 6 5 4 3 2 1 0 5a x 68h r/w zone 2 fan temp limit 7 6 5 4 3 2 1 0 5a x 69h r/w zone 3 fan temp limit 7 6 5 4 3 2 1 0 5a x 3bh r/w zone 4 fan temp limit 7 6 5 4 3 2 1 0 e0 x these are the temperature limits for the individual zones. when the current te mperature equals this limit, the fan will be turned on if it is not already. when the temperature exceed s this limit, the fan speed will be increased according to the algorithm set forth in the auto fan range, pwm frequency register description, default = 90 c = 5ah this register becomes read-only when the ready/lock/start/override register lock bit is set. any further attempts to write to this register shall have no effect. temperature fan temp limit (2?s complement) >127 c 0111 1111 +127 c 0111 1111 +125 c 0111 1101 +90 c (default) 0101 1010 preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 40 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 temperature fan temp limit (2?s complement) +50 c 0011 0010 +25 c 0001 1001 0 c 0000 0000 -50 c 1100 1110 -127 c 1000 0001 table 26 fan temperature limit register - 8-bit two?s complement register 6a-6ch: temperature limit register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock 6ah r/w zone 1 temp absolute limit 7 6 5 4 3 2 1 0 64 x 6bh r/w zone 2 temp absolute limit 7 6 5 4 3 2 1 0 64 x 6ch r/w zone 3 temp absolute limit 7 6 5 4 3 2 1 0 64 x 3dh r/w zone 4 temp absolute limit 7 6 5 4 3 2 1 0 00 x in the auto fan mode, if a zone exceeds the temperature set in the absolute temperature limit register, all of the pwm outputs will increase its duty cycle to 100%. th is is a safety feature that attempts to cool the system if there is a potentia lly catastrophic thermal ev ent. if set to 80h (-128 c), the feature is disabled. default = 100 c = 64h. the pwm will remain at 100% until the assigned temperature zone falls below the absolute temp limit for that zone by an amount equal to the hysteresis value for that zone. these registers become read-only when the ready/lock/start/ov erride register lock bit is set. any further attempts to write to these registers shall have no effect. temperature absolute limit (2?s complement) >127 c 0111 1111 +127 c 0111 1111 +125 c 0111 1101 +100 c (default) 0110 0100 +50 c 0011 0010 +25 c 0001 1001 0 c 0000 0000 -50 c 1100 1110 -127 c 1000 0001 -128 c (disable) 1000 0000 table 27 absolute temperature limit register - 8-bit two?s complement preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 41 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 register 6d-6eh: thermal zone hysteresis register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock 6dh r/w zone 1 and zone 2 hysteresis h1-3 h1-2 h1-1 h1-0 h2-3 h2-2 h2-1 h2-0 44 x 6eh r/w zone 3 and zone 4 hysteresis h3-3 h3-2 h3-1 h3-0 h4-3 h4-2 h4-1 h4-0 44 x if the temperature is above fan temp limit, then dr ops below fan temp limit, the following will occur: ? the fan will remain on, at fan pwm minimum, until the temperature goes a certain amount below fan temp limit. ? the hysteresis registers control this amount. see below table for details, all values from 0 c to 15 c are possible. this register becomes read-only when the ready/lock/start/override register lock bit is set. any further attempts to write to these registers shall have no effect. temperature zone hysteresis hn-[3:0] 0 c 0000 1 c 0001 4 c (default) 0100 10 c 1010 15 c 1111 table 28 zone hysteresis register format register 75h: fan spin-up mode register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock 75h r/w fan spin- up mode tach4 disable tach3/4 disable tach2 disable tach1 disable res pwm3 su pwm2 su pwm1 su 00 x the pwm su bit configures the pwm spin-up mode. if pwm su is cleared the spin-up time will terminate after time programmed by the fan configurat ion register has elapsed. when set to 1, the spin-up time will terminate early if the tach reading interpreted as rpm exceeds the tach minimum rpm va lue or after the time programmed by the fan configuration register has elapsed, which ever occurs first. note that the magnitudes of the tach readings and the limits in the registers represent a time period that is inversely proportional to rpm. this register becomes read-only when the ready/lock/start/override register lock bi t is set. any further attempts to write to this register shall have no effect. preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 42 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 miscellaneous registers registers 19h and 1ah: gpio configuration register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock alert assignment gpio 1 function 19h r/w gpio 1 configuration res res 1 0 gpio 1 bit 2 1 0 00 x gpio 2 function gpio 3 function 1ah r/w gpio 2 configuration gpio 2 bit 2 1 0 gpio 3 bit 2 1 0 00 x gpio pins are multi-function and may be used as input, output, bi -directional or may serve as an alarm pin with alert or therm behavior. this is an open-drain output and a read returns the state of the pi n, a write drives the pin based on the gpio bit. this register becomes read-only when the ready/lock/start/override register lock bi t is set. any further attempts to write to this register shall have no effect. gpio configuration 1 contains two controls. the 1st is the alert assignment and the 2nd is gpio 1 pin definitions. 1. the alert assignment defines which one of the gpio pi ns that will source the alert. the alert assignment supersedes any gpio pin configuration. 2. the gpio 1 function defines the c onfiguration of the gpio 1 pin. the default is to configure the pin as an input. any zone fan temp limit status can be sent to t he pin or the written value of bit 3 can be sent to gpio 1 pin. the read value of bit 3 indicates the level of the gpio 1 pin not the stat e of the gpio register bit. bit field gpio configuration 1 [19h] value function 000 (default) gpio pin read only, output drive always set high. 001 zone 1 therm status, pin = 0, zone 1 exceeds fan temp limit 010 zone 2 therm status, pin = 0, zone 2 exceeds fan temp limit 011 zone 3 therm status, pin = 0, zone 3 exceeds fan temp limit 100 zone 4 therm status, pin = 0, zone 4 exceeds fan temp limit 101 any zone therm status, pin = 0, any zone exceeds fan temp limit 110 gpio pin read only, output drive always set high. 2:0 gpio 1 function 111 gpio pin io mode, output drive set to gpio reg.bit 3. 3 gpio 1 bit read of this bit always returns value of gpio 1 io pin. write to this function sends value to gpio 1 pin when function is io mode. value function 00 (default) no alert function alert disabled 01 alert function sent to gpio 1, pin = 0, alert active 10 alert function sent to gpio 2, pin = 0, alert active 5:4 alert assignment 11 alert function sent to gpio 3, pin = 0, alert active 7:6 res reserved table 29 gpio configuration 1 [19h] gpio configuration 2 contains two controls. the 1st is gpio 2 pin definition and the 2nd is gpio 3 pin definition. 1. the gpio 2 function defines the conf iguration of the gpio 2 pin. the defau lt is to configure the pin as an input. any zone therm status can be sent to the pin or th e written value of bit 7 can be sent to gpio 2 pin. the read value of bit 7 indicates the level of t he gpio 2 pin not the stat e of bit 7 register. 2. the gpio 3 function defines the c onfiguration of the gpio 3 pin. the default is to configure the pin as an input. any zone therm status can be sent to the pin or th e written value of bit 3 can be sent to gpio 3 pin. the read value of bit 3 indicates the level of t he gpio 3 pin not the stat e of bit 3 register preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 43 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 bit field gpio configuration 2 [1ah] value function 000 (default) gpio pin read only output drive always set high. 001 zone 1 therm status, pin = 0, zone 1 exceeds fan temp limit 010 zone 2 therm status, pin = 0, zone 2 exceeds fan temp limit 011 zone 3 therm status, pin = 0, zone 3 exceeds fan temp limit 100 zone 4 therm status, pin = 0, zone 4 exceeds fan temp limit 101 any zone therm status, pin = 0, any zone exceeds fan temp limit 110 gpio pin read only, output drive always set high. 2-0 gpio 3 function 111 gpio pin io mode, output drive set to gpio reg.bit 3. 3 gpio 3 bit read of this bit always returns value of gpio 3 io pin. write to this function sends value to gpio 3 pin when function is io mode. value function 000 (default) gpio pin read only output drive always set high. 001 zone 1 therm status, pin = 0, zone 1 exceeds fan temp limit 010 zone 2 therm status, pin = 0, zone 2 exceeds fan temp limit 011 zone 3 therm status, pin = 0, zone 3 exceeds fan temp limit 100 zone 4 therm status, pin = 0, zone 4 exceeds fan temp limit 101 any zone therm status, pin = 0, any zone exceeds fan temp limit 110 gpio pin read only output drive always set high. 7:4 alert assignment 111 gpio pin io mode output drive set to gpio reg.bit 7. 7 gpio 2 bit read of this bit always returns value of gpio 2 io pin. write to this function sends value to gpio 2 pin when function is io mode. table 30 gpio configuration 2 [1ah] register 3eh: company id register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 3eh r company id 7 6 5 4 3 2 1 0 61 the company id register contains the company identification num ber. for andigilog this is 61h. this number is assigned by intel and is a method for uniquely identifying the part manufacturer . this register is read-only ? a write to this register ha s no effect. register 3fh: version/stepping register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 3fh r version/stepping ver3 ver2 ver1 ver0 4wire peci stp1 stp0 6c the two least significant bits of the version/stepping register [1 :0] contain the current stepping of the ASC7621 silicon. the four most significant bits [7:4] reflect the ASC7621 base devic e number when set to a value of 0110b. for the ASC7621, this register will read 01101100b (6ch). the register is used by application software to identify wh ich device in the hardware monitor family has been implemented in the given system. based on this information, software can determine which registers to read from and write to. further, application software may use the current stepping to implement work-around for bugs found in a specific silicon stepping. this register is read-only ? a writ e to this register has no effect. preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 44 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 register 6fh: test register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value lock 6fh r/w test register res r es res res res res res xen 00h x xor tree test the ASC7621 incorporates a xor tree test mode. when the test mode is enabled by setting the ?xen? bit high in the test register at address 6fh via the smbus, the part will enter xor test mode. since the test mode an xor tr ee, the order of the signals in the tree is not important. smbdat and smbclk are not included in the test tree. connec tions to the xor tree are shown in figure 12. this register becomes read-only when the ready/lock/start/overri de register lock bit is set. an y further attempts to write to this registers sha ll have no effect. figure 12 xor test tree register 70-7fh: vendor specific registers these registers are for vendor specific feat ures, including test registers. they will not default to a specific value on power up. tach1 tach2 tach3 tach4 pwm2 pwm3 xtestout preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 45 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 applications information remote diodes the ASC7621 is designed to work with a variety of remote sensors in the form of the substrate thermal diode of a cpu or graphics controller or a diode-connected transistor. actual diodes are not suited for these measurements. there is some variation in the performance of these diodes, described in terms of its departure from the ideal diode equation. this factor is called diode non- ideality, . nf the equation relating diode temperature to a change in thermal diode voltage with two driving currents is: v be = (nf ) kt q ln( n ) where: nf = diode non-ideality factor, (nominal 1.009). k = boltzman?s constant, (1.38 x 10 -23 ). t = diode junction temperature in kelvins. q = electron charge (1.6 x 10 -19 coulombs). n = ratio of the two driving currents (16). the ASC7621 is designed and trimmed for an expected nf value of 1.009, based on the typical value for the intel pentium? iii and amd athl on?. there is also a tolerance on the value provided. the values for other cpus and the 2n3904 may have different nominal values and tolerances. consult the cpu or gpu manufacturer?s data sheet for the nf factor. table 31 gives a representative sample of w hat one may expect in the range of non-ideality. the trend with cpus is for a lower value with a larger spread. when thermal diode has a non- ideality factor other than 1.009 the difference in temperature reading at a particular temperature may be interpreted with the following equation: t actual = t reported 1.009 n actual ? ? ? ? ? ? ? ? where: reported t = reported temperature in temperature register. actual t = actual remote diode temperature. actual n = selected diode?s non-ideality factor, nf . temperatures are in kelvins or c + 273.15. this equation assumes that the series resistance of the remote diode is the same fo r each. this resistance is given in the data sheet for the cpu and may vary from 2.5 ? to 4.5 ? . although the temperature error caused by non-ideality difference is directly proportional to the difference from 1.008, but a small difference in non-ideality results in a relatively large difference in temperature reading. for example, if there were a 1% tolerance in the non-ideality of a diode it would result in a 2.7 degree difference (at 0c) in the result (0.01 x 273.15). this difference varies with temperature such that a fixed offset value may only be used over a very narrow range. typical correction method required when measuring a wide range of temperature values is to scale the temperature reading in the host firmware. part nf min nf nom nf max series res pentium? iii (cpuid 68h) 1.0057 1.008 1.0125 pentium 4, 130nm 1.001 1.002 1.003 3.64 pentium 4, 90nm 1.011 3.33 pentium 4, 65nm 1.009 4.52 intel pentium m 1.001 5 1.0022 1.0029 3.06 amd athlon? model 6 1.002 1.008 1.016 amd duron? models 7 and 8 1.002 1.008 1.016 amd athlon models 8 and 10 1.0000 1.0037 1.0090 2n3904 1.003 1.0046 1.005 table 31 representative cpu thermal diode and transistor non-ideality factors cpu or asic substrate remote diodes a substrate diode is a parasitic pnp transistor that has its collector tied to ground through the substrate and the base (remote -) and emitter (remote +) brought out to pins. connection to these pins is shown in figure 13. the non-ideality figures in table 31 include the effects of any package resistance and represent the value seen from the cpu socket. the temperature indicated will need to be compensated for the departure from a non-ideality of 1.008. remote + remote - cpu ASC7621 substrate figure 13 cpu remote diode connection preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 46 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 series resistance any external series resistance in the connections from the ASC7621 to the cpu pins should be accounted for in interpreting the results of a measurement. the impact of series resistance on the measured temperature is a result of measurement currents developing offset voltages t hat add to the diode voltage. this is relatively constant with temperature and may be corrected with a fixed value in the offset register. to determine the temperature im pact of resistance is as follows: t r = r s i d /t v or, t r = r s 90 a 230 v/ c = r s 0.391 c/ where: t r = difference in the temperat ure reading from actual. s r = total series resistance of interconnect (both leads). i d = difference in the two diode current levels (90a). v t = scale of temperature vs. v be (230v/c). for example, a total series resistance of 10 ? would give an offset of +3.9c. discrete remote diodes when sensing temperatures other than the cpu or gpu substrate, an npn or pnp transistor may be used. most commonly used are the 2n3904 and 2n3906. these have characteristics similar to the cpu substrate diode with non-ideality around 1.0046. they are connected with base to collector shorted as shown in figure 14. while it is important to minimize the distance to the remote diode to reduce high-frequency noise pickup, they may be located many feet away with proper shielding. shielded, twisted-pair cable is recommended, with the shield connected only at the ASC7621 end as close as possible to the ground pin of the device. as with the cpu substrat e diode, the temperature reported will be subject to the same errors due to non- ideality variation and series resistance. however, the transistor?s die temperature is usually not the temperature of interest and care must be taken to minimize the thermal resistance and physical distance between that temperature and the remote diode. the offset and response time will need to be characterized by the user. board layout considerations the distance between the remote sensor and the ASC7621 should be minimized. all wiring should be defended from high frequency noise sources and a balanced differential layout maintained on remote + and remote -. any noise, both common-mode and differential, induced in the remote diode interconnect may result in an offset in the temperature reported. cir cuit board layout should follow the recommendation of figure 15. basically, use 10-mil lines and spaces with grounds on each side of the differential pair. closer spacing may also be used if required by layout, but the priority is balance of diode path and minimum vias. choose the ground plane closest to the cpu when using the cpu?s remote diode. noise filtering is accomplished by using a bypass capacitor placed as close as possible to the two pairs of ASC7621 remote + and remote - pins. a 1.0nf ceramic capacitor is recommended, but up to 3.3nf may be used. additional filtering takes place within the ASC7621. it is recommended that the following guidelines be used to minimize noise and achieve highest accuracy: 1. place a 0.1f bypass capacitor to digital ground as close as possible to the power pin of the ASC7621. 2. match the trace routing of the remote + and remote - leads and use a 1.0nf filter capacitor close to the ASC7621. use ground runs along side the pair to minimize differential coupling as in figure 15. 3. place the ASC7621 as close to the cpu or gpu remote diode leads as possible to minimize noise and series resistance. 4. avoid running diode connections close to or in parallel with high-speed busses or 12v, staying at least 2cm away. 10 mil line remote + 10 mil space remote - gnd gnd remote - 2n3906 remote + ASC7621 remote - 2n3904 remote + ASC7621 figure 14 discrete remote diode connection figure 15 recommended remote diode circuit board interconnect preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 47 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 5. avoid running diode connections close to on-board switching power supply inductors. 6. pc board leakage should be minimized by maintaining minimum trace spacing and covering traces over their full length with solder mask. thermal considerations the temperature of the asc7 621 will be close to that of the pc board on which it is mounted. conduction through the leads is the primary path for heat flow. the reported local sensor is very close to the circuit board temperature and typically between the board and ambient. in order to measure pc board temperature in an area of interest, such as the area around the cpu where voltage regulator components generate significant heat, a remote diode-connected transistor should be used. a surface- mount sot-23 or sot-223 is recommended. the small size is advantageous in minimizing response time because of its low thermal mass, but at the same time it has low surface area and a high thermal resistance to ambient air. a compromise must be achieved between minimizing thermal mass and increasing the surface area to lower the junction-to-ambient thermal resistance. in order to sense temperat ure of air-flows near board- mounted heat sources, such as memory modules, the sensor should be mounted ab ove the pc board. a to-92 packaged transistor is recommended. the power consumption of the ASC7621 is relatively low and should have little self-heating effect on the local sensor reading. at the hi ghest measurement rate the dissipation is less than 2mw, resulting in only a few tenths of a degree rise. evaluation board the andigilog smbus evb provides a platform for evaluation of the operational characteristics of the asc7511, asc7512 and ASC7621. the board features a graphical user interface (gui) to control and monitor all activities and readings of these parts. the provided software will run on a windows xp?-based desktop or laptop pc with a usb port. in addition to being a self-contained fan speed control demonstration, it may be connected into an operating pc?s fan and cpu diode to evaluate various settings under real operating conditions without the need to adjust bios code. after optimization, the settings may be programmed into the system. features: ? interactive gui for setting limits and operational configuration ? asc7512 and ASC7621 automatic fan control ? powered and operated from the usb port ? support for reading or writing to any register ? user-defined, time-stamped logging of any registers, saved in spreadsheet-compatible format ? graphical readouts: ? temperature and alarms ? fan rpm ? automatic fan control state ? voltage ? selectable on-board 2n3904 or wired remote diode ? headers for 2-, 3- and 4-wire fans with pwm for asc7512 ? headers for 3 4-wire fans for ASC7621 ? saving of register setting configurations ? led indicators of pin alarm states ? optional use of external 12v fan power for higher current fans ? optional connection to off-board smbus clients application diagrams the ASC7621 may be easily adapted to 2-, 3- or 4-wire fans for precise, wider-range fan speed control when compared to variable dc drive. up to four fans may be controlled. fans 1 and 2 are independent. fan 3 is independent and may be tied to fan 4 for speed control. separate tachometer readings may be reported for all four. application diagram in figure 16 shows connections to four 4-wire fans. external fets may be added to the pwm output to drive 3-wire fans. preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 48 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 figure 16 application diagram remote 1+ remote 1- cpu substrate remote 2 - remote 2 + vccp 2.5v 5v 12v 3.3v gnd gpio1 gpio2 gpio3 peci vtt smbdat smbclk tach 1 pwm 1 tach 2 pwm 2 tach 3 pwm 3 tach 4 gpio / alerts peci vtt smbus 1nf 1nf 0.1f 100pf 2n3904 12v 10k ? 15k ? 7.5k ? 0.01f 12v 10k ? 15k ? 7.5k ? 0.01f 12v 10k ? 15k ? 7.5k ? 0.01f 12v 10k ? 15k ? 7.5k ? 0.01f ASC7621 vccp 2.5v 5v 12v 3.3v preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice - 49 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 physical dimensions inches unless otherwise noted 24-lead molded qsop package notes: 1. pb-free 2. co-planarity is 0 to 0.004? max 3. package surface finish ? matte (vdi #24~27) 4. all dimensions exclude mold flash 5. the lead width, b, to be determined at 0.0075? from the lead tip symbol min max a 0.054 0.068 a1 0.004 0.0098 b 0.008 0.012 d 0.337 0.344 e1 0.150 0.157 e 0.229 0.244 e 0.025 bsc c 0.0075 0.0098 l 0.016 0.034 x 0.0325 ref 1 0 8 2 7 bsc x e pin 1 b a1 a 0.015 0.004 x 45 1 2 l detail ?a? gauge plane seating plane 0.010 c detail ?a? d e e1 x e pin 1 b a1 a 0.015 0.004 x 45 1 2 l detail ?a? gauge plane seating plane 0.010 c detail ?a? d e e1 preliminary specific ation ? subject to change without notice preliminary specific ation ? subject to change without notice andigilog, inc. 8380 s. kyrene rd., suite 101 tempe, arizona 85284 tel: (480) 940-6200 fax: (480) 940-4255 - 50 - ? andigilog, inc. 2006 www.andigilog.com october 2006 - 70a06010 ASC7621 data sheet classifications preliminary specification this classification is shown on the heading of each page of a specification for produc ts that are either under development (design and qualification), or in the formative planning stages. andigilog reserves the right to change or discontinue these products without notice. new release specification this classification is shown on the heading of the first page only of a specification for products that are either under the later stages of development (characterization an d qualification), or in the early weeks of release to production. andigilog reserves the right to change the specification and information for these products without notice. fully released specification fully released datasheets do not contain any classifica tion in the first page header. these documents contain specification on products that are in full production. andigilog will not change any guaranteed limits without written notice to the customers. obsolete datasheets that were written prior to january 1, 2001 without any header classification information should be considered as ob solete and non-active specifications, or in the best case as preliminary specifications. pentium? is a trademark of intel corporation athlon? and duron? are trad emarks of amd corporation sst and simple serial transport are trademarks of analog devices, inc. windows xp? is a trademark of microsoft, inc. life support policy andigilog's products are not authorized for use as critical components in life support devices or systems without the express written approval of the president and general counsel of andigilog, inc. as used herein: 1. life support devices or systems are dev ices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect it s safety or effectiveness. |
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